arm64: Make exceptions work
BUG=chrome-os-partner:31515 BRANCH=None TEST=test_exception generates a page fault which is handled by the exception handler and execution continues after eret from the exception Change-Id: Ie550492d2ed21b2c3009b5627f1e1a37429e6af0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e29fe77745d10e840c02498e54a0c53835530e5e Original-Change-Id: I29b7dabaece9b11a04ee3628d83513d30eb07b1d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213661 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Furquan Shaikh
Patrick Georgi
parent
1af7b5ddf1
commit
69761cd165
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@ -32,98 +32,110 @@
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#include <arch/cache.h>
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#include <arch/exception.h>
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#include <console/console.h>
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#include <arch/lib_helpers.h>
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void exception_sync_el0(uint64_t *regs, uint64_t esr);
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void exception_irq_el0(uint64_t *regs, uint64_t esr);
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void exception_fiq_el0(uint64_t *regs, uint64_t esr);
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void exception_serror_el0(uint64_t *regs, uint64_t esr);
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void exception_sync(uint64_t *regs, uint64_t esr);
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void exception_irq(uint64_t *regs, uint64_t esr);
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void exception_fiq(uint64_t *regs, uint64_t esr);
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void exception_serror(uint64_t *regs, uint64_t esr);
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static unsigned int test_exc;
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static void print_regs(uint64_t *regs)
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struct exception_handler_info
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{
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const char *name;
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};
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enum {
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EXC_SYNC_SP0 = 0,
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EXC_IRQ_SP0,
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EXC_FIQ_SP0,
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EXC_SERROR_SP0,
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EXC_SYNC_SP3,
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EXC_IRQ_SP3,
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EXC_FIQ_SP3,
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EXC_SERROR_SP3,
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EXC_SYNC_ELX_64,
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EXC_IRQ_ELX_64,
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EXC_FIQ_ELX_64,
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EXC_SERROR_ELX_64,
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EXC_SYNC_ELX_32,
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EXC_IRQ_ELX_32,
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EXC_FIQ_ELX_32,
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EXC_SERROR_ELX_32,
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EXC_COUNT
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};
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static struct exception_handler_info exceptions[EXC_COUNT] = {
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[EXC_SYNC_SP0] = { "_sync_sp_el0" },
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[EXC_IRQ_SP0] = { "_irq_sp_el0" },
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[EXC_FIQ_SP0] = { "_fiq_sp_el0" },
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[EXC_SERROR_SP0] = {"_serror_sp_el0"},
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[EXC_SYNC_SP3] = { "_sync_sp_el3" },
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[EXC_IRQ_SP3] = { "_irq_sp_el3" },
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[EXC_FIQ_SP3] = { "_fiq_sp_el3" },
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[EXC_SERROR_SP3] = {"_serror_sp_el3"},
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[EXC_SYNC_ELX_64] = { "_sync_elx_64" },
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[EXC_IRQ_ELX_64] = { "_irq_elx_64" },
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[EXC_FIQ_ELX_64] = { "_fiq_elx_64" },
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[EXC_SERROR_ELX_64] = {"_serror_elx_64"},
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[EXC_SYNC_ELX_32] = { "_sync_elx_32" },
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[EXC_IRQ_ELX_32] = { "_irq_elx_32" },
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[EXC_FIQ_ELX_32] = { "_fiq_elx_32" },
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[EXC_SERROR_ELX_32] = {"_serror_elx_32"},
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};
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static void print_regs(struct exception_state *state)
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{
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int i;
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uint64_t far_el3;
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/* ELR contains the restart PC at target exception level */
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printk(BIOS_ERR, "ELR = 0x%016llx ", regs[0]);
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printk(BIOS_ERR, "X00 = 0x%016llx\n", regs[1]);
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far_el3 = raw_read_far_el3();
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for (i = 2; i < 31; i+=2) {
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printk(BIOS_ERR, "X%02d = 0x%016llx ", i - 1, regs[i]);
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printk(BIOS_ERR, "X%02d = 0x%016llx\n", i, regs[i + 1]);
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printk(BIOS_DEBUG, "ELR = 0x%016llx\n", state->elr);
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printk(BIOS_DEBUG, "ESR = 0x%08llx\n", state->esr);
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printk(BIOS_DEBUG, "FAR_EL3 = 0x%016llx\n", far_el3);
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for (i = 0; i < 31; i++)
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printk(BIOS_DEBUG, "X%02d = 0x%016llx\n", i, state->regs[i]);
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}
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void exception_dispatch(struct exception_state *state, int idx)
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{
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if (idx >= EXC_COUNT) {
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printk(BIOS_DEBUG, "Bad exception index %d.\n", idx);
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} else {
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struct exception_handler_info *info = &exceptions[idx];
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if (info->name)
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printk(BIOS_DEBUG, "exception %s\n", info->name);
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else
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printk(BIOS_DEBUG, "exception _not_used.\n");
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}
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print_regs(state);
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if (test_exc) {
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state->elr += 4;
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test_exc = 0;
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printk(BIOS_DEBUG, "new ELR = 0x%016llx\n", state->elr);
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} else
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die("exception");
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}
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void exception_sync_el0(uint64_t *regs, uint64_t esr)
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static uint64_t test_exception(void)
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{
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printk(BIOS_ERR, "exception _sync_el0 (ESR = 0x%08llx)\n", esr);
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print_regs(regs);
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die("exception");
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}
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uint64_t *a = (uint64_t *)0xfffffffff0000000ULL;
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void exception_irq_el0(uint64_t *regs, uint64_t esr)
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{
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printk(BIOS_ERR, "exception _irq_el0 (ESR = 0x%08llx)\n", esr);
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print_regs(regs);
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die("exception");
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}
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test_exc = 1;
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void exception_fiq_el0(uint64_t *regs, uint64_t esr)
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{
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printk(BIOS_ERR, "exception _fiq_el0 (ESR = 0x%08llx)\n", esr);
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print_regs(regs);
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die("exception");
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}
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printk(BIOS_DEBUG, "%llx\n", *a);
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void exception_serror_el0(uint64_t *regs, uint64_t esr)
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{
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printk(BIOS_ERR, "exception _serror_el0 (ESR = 0x%08llx)\n", esr);
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print_regs(regs);
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die("exception");
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}
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void exception_sync(uint64_t *regs, uint64_t esr)
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{
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printk(BIOS_ERR, "exception _sync (ESR = 0x%08llx)\n", esr);
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print_regs(regs);
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die("exception");
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}
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void exception_irq(uint64_t *regs, uint64_t esr)
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{
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printk(BIOS_ERR, "exception _irq (ESR = 0x%08llx)\n", esr);
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print_regs(regs);
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die("exception");
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}
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void exception_fiq(uint64_t *regs, uint64_t esr)
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{
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printk(BIOS_ERR, "exception _fiq (ESR = 0x%08llx)\n", esr);
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print_regs(regs);
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die("exception");
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}
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void exception_serror(uint64_t *regs, uint64_t esr)
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{
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printk(BIOS_ERR, "exception _serror (ESR = 0x%08llx)\n", esr);
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print_regs(regs);
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die("exception");
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return 0;
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}
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void exception_init(void)
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{
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//uint32_t sctlr = read_sctlr();
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/* Handle exceptions in ARM mode. */
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//sctlr &= ~SCTLR_TE;
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/* Set V=0 in SCTLR so VBAR points to the exception vector table. */
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//sctlr &= ~SCTLR_V;
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/* Enforce alignment temporarily. */
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//write_sctlr(sctlr);
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extern void *exception_table;
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extern uint32_t exception_table[];
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set_vbar((uintptr_t)exception_table);
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set_vbar(&exception_table);
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printk(BIOS_DEBUG, "Exception handlers installed.\n");
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printk(BIOS_DEBUG, "ARM64: Exception handlers installed.\n");
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printk(BIOS_DEBUG, "ARM64: Testing exception\n");
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test_exception();
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printk(BIOS_DEBUG, "ARM64: Done test exception\n");
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}
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@ -29,75 +29,98 @@
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#include <arch/asm.h>
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.text
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.macro eentry lbl id
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.align 7
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\lbl:
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stp x30, xzr, [sp, #-16]!
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bl exception_prologue
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mov x1, \id
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bl exception_handler
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.endm
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.align 11
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.align 11
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.global exception_table
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exception_table:
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.align 7
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bl exception_prologue
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bl exception_sync_el0
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.align 7
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bl exception_prologue
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bl exception_irq_el0
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.align 7
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bl exception_prologue
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bl exception_fiq_el0
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.align 7
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bl exception_prologue
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bl exception_serror_el0
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.align 7
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bl exception_prologue
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bl exception_sync
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.align 7
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bl exception_prologue
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bl exception_irq
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.align 7
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bl exception_prologue
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bl exception_fiq
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.align 7
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bl exception_prologue
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bl exception_serror
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/*
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* Save state (register file + ELR) to stack
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* and set arguments x0 and x1 for exception call
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*/
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ENTRY(exception_prologue)
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stp x29, x30, [sp, #-16]!
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stp x27, x28, [sp, #-16]!
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stp x25, x26, [sp, #-16]!
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stp x23, x24, [sp, #-16]!
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stp x21, x22, [sp, #-16]!
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stp x19, x20, [sp, #-16]!
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stp x17, x18, [sp, #-16]!
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stp x15, x16, [sp, #-16]!
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stp x13, x14, [sp, #-16]!
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stp x11, x12, [sp, #-16]!
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stp x9, x10, [sp, #-16]!
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stp x7, x8, [sp, #-16]!
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stp x5, x6, [sp, #-16]!
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stp x3, x4, [sp, #-16]!
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stp x1, x2, [sp, #-16]!
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eentry sync_el3_sp0,#0
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eentry irq_el3_sp0,#1
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eentry fiq_el3_sp0,#2
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eentry serror_el3_sp0,#3
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eentry sync_el3_sp3,#4
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eentry irq_el3_sp3,#5
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eentry fiq_el3_sp3,#6
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eentry serror_el3_sp3,#7
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eentry sync_elx_64,#8
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eentry irq_elx_64,#9
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eentry fiq_elx_64,#10
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eentry serror_elx_64,#11
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eentry sync_elx_32,#12
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eentry irq_elx_32,#13
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eentry fiq_elx_32,#14
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eentry serror_elx_32,#15
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/* FIXME: Don't assume always running in EL2 */
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mrs x1, elr_el2
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stp x1, x0, [sp, #-16]!
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exception_prologue:
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/* Save all registers x0-x29 */
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stp x28, x29, [sp, #-16]!
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stp x26, x27, [sp, #-16]!
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stp x24, x25, [sp, #-16]!
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stp x22, x23, [sp, #-16]!
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stp x20, x21, [sp, #-16]!
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stp x18, x19, [sp, #-16]!
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stp x16, x17, [sp, #-16]!
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stp x14, x15, [sp, #-16]!
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stp x12, x13, [sp, #-16]!
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stp x10, x11, [sp, #-16]!
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stp x8, x9, [sp, #-16]!
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stp x6, x7, [sp, #-16]!
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stp x4, x5, [sp, #-16]!
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stp x2, x3, [sp, #-16]!
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stp x0, x1, [sp, #-16]!
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mrs x1, esr_el2
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mov x0, sp
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/* Save the exception reason on stack */
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mrs x1, esr_el3
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/* Save the return address on stack */
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mrs x0, elr_el3
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stp x0, x1, [sp, #-16]!
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ret
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ENDPROC(exception_prologue)
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.global exception_stack_end
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exception_stack_end:
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.quad 0
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exception_handler:
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.word 0
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/* Save address of saved registers into x0
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* This acts as first argument to exception_dispatch
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*/
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mov x0, sp
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bl exception_dispatch
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/* Pop return address and exception reason saved on stack */
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ldp x0, x1, [sp], #16
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msr elr_el3, x0
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msr esr_el3, x1
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/* Pop registers x0-x30 */
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ldp x0, x1, [sp], #16
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ldp x2, x3, [sp], #16
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ldp x4, x5, [sp], #16
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ldp x6, x7, [sp], #16
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ldp x8, x9, [sp], #16
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ldp x10, x11, [sp], #16
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ldp x12, x13, [sp], #16
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ldp x14, x15, [sp], #16
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ldp x16, x17, [sp], #16
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ldp x18, x19, [sp], #16
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ldp x20, x21, [sp], #16
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ldp x22, x23, [sp], #16
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ldp x24, x25, [sp], #16
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ldp x26, x27, [sp], #16
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ldp x28, x29, [sp], #16
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ldp x30, xzr, [sp], #16
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eret
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.global set_vbar
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set_vbar:
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msr vbar_el2, x0
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/* Initialize the exception table address in vbar for EL3 */
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msr vbar_el3, x0
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dsb sy
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isb
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ret
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@ -32,7 +32,15 @@
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#include <stdint.h>
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struct exception_state
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{
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uint64_t elr;
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uint64_t esr;
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uint64_t regs[31];
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} __attribute__((packed));
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void exception_init(void);
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void set_vbar(uint64_t vbar);
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void set_vbar(void *vbar);
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void exception_dispatch(struct exception_state *state, int idx);
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#endif
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