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soc/intel/alderlake: Add ADLP 242 power configurations 

Add ADLP 242 sku power related settings, which follow the settings of
ADLP 282 sku (both are 15w).

BUG=b:201253904
TEST=Build and check fsp log to confirm the settings are set properly.

Change-Id: I829dd690c22d167a507b1910106da06b275cec09
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
Tracy Wu 2021-09-27 16:48:32 +08:00 committed by Patrick Georgi
parent dee834aafc
commit 697d6a81c2
4 changed files with 14 additions and 0 deletions
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2
src/soc/intel/alderlake/chip.h
View File

@ -27,6 +27,7 @@ enum soc_intel_alderlake_power_limits {
ADL_P_682_45W_CORE,
ADL_M_282_CORE,
ADL_M_242_CORE,
ADL_P_242_CORE,
ADL_POWER_LIMITS_COUNT
};
@ -45,6 +46,7 @@ static const struct {
enum soc_intel_alderlake_cpu_tdps cpu_tdp;
} cpuid_to_adl[] = {
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, ADL_P_282_CORE, TDP_15W },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, ADL_P_242_CORE, TDP_15W },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_482_CORE, TDP_28W },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_45W_CORE, TDP_45W },

5
src/soc/intel/alderlake/chipset.cb
View File

@ -37,6 +37,11 @@ chip soc/intel/alderlake
.tdp_pl4 = 68,
}"
register "power_limits_config[ADL_P_242_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 55,
.tdp_pl4 = 123,
}"
device domain 0 on
device gpio 0 alias pch_gpio on end

3
src/soc/intel/alderlake/fsp_params.c
View File

@ -41,6 +41,7 @@
#define MILLIAMPS_TO_AMPS 1000
#define ICC_MAX_ID_ADL_P_3_MA 34250
#define ICC_MAX_ID_ADL_P_5_MA 32000
#define ICC_MAX_ID_ADL_P_6_MA 32000
#define ICC_MAX_ID_ADL_P_7_MA 32000
/*
@ -305,6 +306,8 @@ static uint16_t get_vccin_aux_imon_iccmax(void)
return ICC_MAX_ID_ADL_P_3_MA;
case PCI_DEVICE_ID_INTEL_ADL_P_ID_5:
return ICC_MAX_ID_ADL_P_5_MA;
case PCI_DEVICE_ID_INTEL_ADL_P_ID_6:
return ICC_MAX_ID_ADL_P_6_MA;
case PCI_DEVICE_ID_INTEL_ADL_P_ID_7:
return ICC_MAX_ID_ADL_P_7_MA;
default:

4
src/soc/intel/alderlake/vr_config.c
View File

@ -50,24 +50,28 @@ static uint32_t load_table(const struct vr_lookup *tbl, const int tbl_entries, c
static const struct vr_lookup vr_config_ll[] = {
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
};
static const struct vr_lookup vr_config_icc[] = {
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_ICC(160, 50) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_ICC(109, 50) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
};
static const struct vr_lookup vr_config_tdc_timewindow[] = {
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
};
static const struct vr_lookup vr_config_tdc_currentlimit[] = {
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
};