soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER
Rename SPIROM_BASE_ADDRESS_REGISTER to SPI_BASE_ADDRESS_REGISTER to clarify that this isn't the address the SPI flash gets mapped, but the address of the SPI controller MMIO region. This also aligns the register name with the PPR. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
parent
6f73a202d3
commit
697fa74027
|
@ -9,7 +9,7 @@
|
|||
#define LPC_LDRQ0_PU_EN BIT(10)
|
||||
#define LPC_LDRQ0_PD_EN BIT(9)
|
||||
|
||||
#define SPIROM_BASE_ADDRESS_REGISTER 0xa0
|
||||
#define SPI_BASE_ADDRESS_REGISTER 0xa0
|
||||
#define SPI_BASE_ALIGNMENT BIT(8)
|
||||
#define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7))
|
||||
#define PSP_SPI_MMIO_SEL BIT(4)
|
||||
|
|
|
@ -124,9 +124,9 @@ static void lpc_set_resources(struct device *dev)
|
|||
|
||||
/* Special case. The SpiRomEnable and other enables should STAY set. */
|
||||
res = find_resource(dev, 2);
|
||||
spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
|
||||
spi_enable_bits = pci_read_config32(dev, SPI_BASE_ADDRESS_REGISTER);
|
||||
spi_enable_bits &= SPI_BASE_ALIGNMENT - 1;
|
||||
pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER,
|
||||
pci_write_config32(dev, SPI_BASE_ADDRESS_REGISTER,
|
||||
res->base | spi_enable_bits);
|
||||
|
||||
pci_dev_set_resources(dev);
|
||||
|
|
|
@ -187,13 +187,13 @@ uintptr_t lpc_spibase(void)
|
|||
u32 base, enables;
|
||||
|
||||
/* Make sure the base address is predictable */
|
||||
base = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER);
|
||||
base = pci_read_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER);
|
||||
enables = base & SPI_PRESERVE_BITS;
|
||||
base &= ~(SPI_PRESERVE_BITS | SPI_BASE_RESERVED);
|
||||
|
||||
if (!base) {
|
||||
base = SPI_BASE_ADDRESS;
|
||||
pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER,
|
||||
pci_write_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER,
|
||||
base | enables | SPI_ROM_ENABLE);
|
||||
/* PCI_COMMAND_MEMORY is read-only and enabled. */
|
||||
}
|
||||
|
@ -233,8 +233,8 @@ void lpc_tpm_decode_spi(void)
|
|||
|
||||
/* Route TPM accesses to SPI */
|
||||
u32 spibase = pci_read_config32(_LPCB_DEV,
|
||||
SPIROM_BASE_ADDRESS_REGISTER);
|
||||
pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase
|
||||
SPI_BASE_ADDRESS_REGISTER);
|
||||
pci_write_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER, spibase
|
||||
| ROUTE_TPM_2_SPI);
|
||||
}
|
||||
|
||||
|
@ -310,7 +310,7 @@ uintptr_t lpc_get_spibase(void)
|
|||
{
|
||||
u32 base;
|
||||
|
||||
base = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER);
|
||||
base = pci_read_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER);
|
||||
base = ALIGN_DOWN(base, SPI_BASE_ALIGNMENT);
|
||||
return (uintptr_t)base;
|
||||
}
|
||||
|
@ -319,12 +319,12 @@ void lpc_set_spibase(uint32_t base)
|
|||
{
|
||||
uint32_t reg32;
|
||||
|
||||
reg32 = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER);
|
||||
reg32 = pci_read_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER);
|
||||
|
||||
reg32 &= SPI_BASE_ALIGNMENT - 1; /* preserve only reserved, enables */
|
||||
reg32 |= ALIGN_DOWN(base, SPI_BASE_ALIGNMENT);
|
||||
|
||||
pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32);
|
||||
pci_write_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER, reg32);
|
||||
}
|
||||
|
||||
void lpc_enable_spi_rom(uint32_t enable)
|
||||
|
@ -334,12 +334,12 @@ void lpc_enable_spi_rom(uint32_t enable)
|
|||
/* only two types of CS# enables are allowed */
|
||||
enable &= SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE;
|
||||
|
||||
reg32 = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER);
|
||||
reg32 = pci_read_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER);
|
||||
|
||||
reg32 &= ~(SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE);
|
||||
reg32 |= enable;
|
||||
|
||||
pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32);
|
||||
pci_write_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER, reg32);
|
||||
}
|
||||
|
||||
static void lpc_enable_controller(void)
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
#ifndef AMD_PICASSO_LPC_H
|
||||
#define AMD_PICASSO_LPC_H
|
||||
|
||||
#define SPIROM_BASE_ADDRESS_REGISTER 0xa0
|
||||
#define SPI_BASE_ADDRESS_REGISTER 0xa0
|
||||
#define SPI_BASE_ALIGNMENT BIT(8)
|
||||
#define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7))
|
||||
#define PSP_SPI_MMIO_SEL BIT(4)
|
||||
|
|
|
@ -11,7 +11,7 @@
|
|||
#define LPC_LDRQ0_PU_EN BIT(10)
|
||||
#define LPC_LDRQ0_PD_EN BIT(9)
|
||||
|
||||
#define SPIROM_BASE_ADDRESS_REGISTER 0xa0
|
||||
#define SPI_BASE_ADDRESS_REGISTER 0xa0
|
||||
#define SPI_BASE_ALIGNMENT BIT(8)
|
||||
#define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7))
|
||||
#define PSP_SPI_MMIO_SEL BIT(4)
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
#ifndef AMD_STONEYRIDGE_LPC_H
|
||||
#define AMD_STONEYRIDGE_LPC_H
|
||||
|
||||
#define SPIROM_BASE_ADDRESS_REGISTER 0xa0
|
||||
#define SPI_BASE_ADDRESS_REGISTER 0xa0
|
||||
#define SPI_BASE_ALIGNMENT BIT(6)
|
||||
#define SPI_BASE_RESERVED (BIT(4) | BIT(5))
|
||||
#define ROUTE_TPM_2_SPI BIT(3)
|
||||
|
|
Loading…
Reference in New Issue