mainboard/google/kahlee: Use 66MHz SPI clock for fast read

Looking at the 100MHz signal, we were violating the timing requirements.
66MHz still isn't great, but it's a good tradeoff between improving
the signal and losing boot speed time.

This slows down the boot time by about 20mS.

BUG=b:109583457
TEST=Boot grunt, look at signal on scope

Change-Id: I7ce70c992822dd17c5877226e74c1890660768c6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/mainboard/google/kahlee/bootblock/bootblock.c

@@ -44,7 +44,7 @@ void bootblock_mainboard_init(void)
 
 	/* Set SPI speeds before verstage. Needed for TPM */
 	sb_set_spi100(SPI_SPEED_33M,		/* Normal */
-			SPI_SPEED_100M,		/* Fast   */
+			SPI_SPEED_66M,		/* Fast   */
 			SPI_SPEED_66M,		/* AltIO  */
 			SPI_SPEED_66M);		/* TPM    */