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cpu/amd/pi/00730F01/fixme: use coreboot's PCI access functions 

Use coreboot's native PCI access functions instead of using the
vendorcode's PCI access functions to set up the CPU IO routing in
function 1 of the HT PCI device. This file still has room for
improvement, but at least it's now using coreboot-native functionality.
Stoneyridge has a nicer implementation, but looking into possibly
unifying those is out of scope for this patch.

TEST=None

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieecc0e5f6576a838d79220b061de81e21b5d976c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This commit is contained in:
Felix Held 2023-04-20 14:08:32 +02:00
parent cc827d9aab
commit 69ababcbf6
1 changed files with 13 additions and 36 deletions
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49
src/cpu/amd/pi/00730F01/fixme.c
View File

@ -1,54 +1,31 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/pci_devs.h>
#include <arch/hpet.h> #include <arch/hpet.h>
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#include <device/pci.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
#include <AGESA.h>
#include <amdlib.h>
void amd_initcpuio(void) void amd_initcpuio(void)
{ {
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */ /* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); pci_write_config32(_SOC_DEV(0x18, 1), 0xf4, 1);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions. * set to non-posted regions. Last address before processor local APIC
* at FEE00000, set NP (non-posted) bit.
*/ */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); pci_write_config32(_SOC_DEV(0x18, 1), 0x84, 0x00fedf00 | (1 << 7));
/* last address before processor local APIC at FEE00000 */
PciData = 0x00FEDF00;
/* set NP (non-posted) bit */
PciData |= 1 << 7;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
/* lowest NP address is HPET at FED00000 */ /* lowest NP address is HPET at FED00000 */
PciData = (HPET_BASE_ADDRESS >> 8) | 3; pci_write_config32(_SOC_DEV(0x18, 1), 0x80, (HPET_BASE_ADDRESS >> 8) | 3);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */ /* Map the remaining PCI hole as posted MMIO. 0xfecf0000 is the last
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); address before non-posted range */
PciData = 0x00FECF00; /* last address before non-posted range */ pci_write_config32(_SOC_DEV(0x18, 1), 0x8c, 0x00fecf00);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); pci_write_config32(_SOC_DEV(0x18, 1), 0x88, (get_top_of_mem_below_4gb() >> 8) | 3);
LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */ /* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); pci_write_config32(_SOC_DEV(0x18, 1), 0xc4, 0x0000f000);
PciData = 0x0000F000; pci_write_config32(_SOC_DEV(0x18, 1), 0xc0, 0x00000003);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
} }