mb/{intel/google}: Move CNVi ASL entry from static DSDT to dynamic SSDT generation

This changes uses drivers/intel/wifi chip for CNVi device to ensure that:
1. Correct device name shows in ACPI name space
2. Correct wake up shows in cat /proc/acpi/wakeup
3. Remove cnvi.asl from soc/intel/cannonlake

Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/google/sarien/variants/arcada/devicetree.cb

@@ -110,6 +110,10 @@ chip soc/intel/cannonlake
 		device pci 12.6 off end # GSPI #2
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
+		chip drivers/intel/wifi
+			register "wake" = "PME_B0_EN_BIT"
+			device pci 14.3 on  end # CNVi wifi
+		end
 		device pci 14.5 off end # SDCard
 		device pci 15.0 on  end # I2C #0
 		device pci 15.1 on

src/mainboard/google/sarien/variants/sarien/devicetree.cb

@@ -110,6 +110,10 @@ chip soc/intel/cannonlake
 		device pci 12.6 off end # GSPI #2
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
+		chip drivers/intel/wifi
+			register "wake" = "PME_B0_EN_BIT"
+			device pci 14.3 on  end # CNVi wifi
+		end
 		device pci 14.5 off end # SDCard
 		device pci 15.0 on  end # I2C #0
 		device pci 15.1 on

src/mainboard/google/zoombini/variants/baseboard/devicetree.cb

@@ -71,6 +71,10 @@ chip soc/intel/cannonlake
 		device pci 12.6 off end # GSPI #2
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
+		chip drivers/intel/wifi
+			register "wake" = "PME_B0_EN_BIT"
+			device pci 14.3 on  end # CNVi wifi
+		end
 		device pci 14.5 on  end # SDCard
 		device pci 15.0 on  end # I2C #0
 		device pci 15.1 on  end # I2C #1

src/mainboard/google/zoombini/variants/meowth/devicetree.cb

@@ -92,6 +92,10 @@ chip soc/intel/cannonlake
 		device pci 12.6 off end # GSPI #2
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
+		chip drivers/intel/wifi
+			register "wake" = "PME_B0_EN_BIT"
+			device pci 14.3 on  end # CNVi wifi
+		end
 		device pci 14.5 off end # SDCard
 		device pci 15.0 on
 			chip drivers/i2c/hid

src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb

@@ -95,7 +95,10 @@ chip soc/intel/cannonlake
 		device pci 12.6 off end # GSPI #2
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
+		chip drivers/intel/wifi
+			register "wake" = "PME_B0_EN_BIT"
 			device pci 14.3 on  end # CNVi wifi
+		end
 		device pci 14.5 on  end # SDCard
 		device pci 15.0 on  end # I2C #0
 		device pci 15.1 on  end # I2C #1

src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb

@@ -79,7 +79,10 @@ chip soc/intel/cannonlake
 		device pci 12.6 off end # GSPI #2
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
+		chip drivers/intel/wifi
+			register "wake" = "PME_B0_EN_BIT"
 			device pci 14.3 on  end # CNVi wifi
+		end
 		device pci 14.5 on  end # SDCard
 		device pci 15.0 on
 			chip drivers/i2c/hid

src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb

@@ -111,7 +111,10 @@ chip soc/intel/cannonlake
 		device pci 12.6 off end # GSPI #2
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
+		chip drivers/intel/wifi
+			register "wake" = "PME_B0_EN_BIT"
 			device pci 14.3 on  end # CNVi wifi
+		end
 		device pci 14.5 on  end # SDCard
 		device pci 15.0 on  end # I2C 0
 		device pci 15.1 on  end # I2C #1

src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb

@@ -95,7 +95,10 @@ chip soc/intel/cannonlake
 		device pci 12.6 off end # GSPI #2
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
+		chip drivers/intel/wifi
+			register "wake" = "PME_B0_EN_BIT"
 			device pci 14.3 on  end # CNVi wifi
+		end
 		device pci 14.5 on  end # SDCard
 		device pci 15.0 on  end # I2C #0
 		device pci 15.1 on  end # I2C #1

src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb

@@ -86,7 +86,10 @@ chip soc/intel/cannonlake
 		device pci 12.6 off end # GSPI #2
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
+		chip drivers/intel/wifi
+			register "wake" = "PME_B0_EN_BIT"
 			device pci 14.3 on  end # CNVi wifi
+		end
 		device pci 14.5 on  end # SDCard
 		device pci 15.0 on  end # I2C #0
 		device pci 15.1 on  end # I2C #1

src/soc/intel/cannonlake/acpi/cnvi.asl

@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/pm.h>
-
-/* CNVi Controller 0:14.3 */
-Device (CNVI) {
-	 Name(_ADR, 0x00140003)
-
-	Name (_S3D, 3)  /* D3 supported in S3 */
-	Name (_S0W, 3)  /* D3 can wake device in S0 */
-	Name (_S3W, 3)  /* D3 can wake system from S3 */
-
-	Name (_PRW, Package() { PME_B0_EN_BIT, 3 })
-
-	Method (_STA, 0)
-	{
-		Return (0xF)
-	}
-}

src/soc/intel/cannonlake/acpi/southbridge.asl

@@ -60,8 +60,5 @@
 /* PCI _OSC */
 #include <soc/intel/common/acpi/pci_osc.asl>
 
-/* CNVi */
-#include "cnvi.asl"
-
 /* GBe 0:1f.6 */
 #include "pch_glan.asl"

src/soc/intel/cannonlake/chip.h

@@ -25,6 +25,7 @@
 #include <soc/gpio.h>
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
+#include <soc/pm.h>
 #include <soc/pmc.h>
 #include <soc/serialio.h>
 #include <soc/usb.h>