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mb/google/dedede/var/sasukette: Update DPTF parameters 

Update DPTF parameters from internal thermal team.

BUG=b:180875580
BRANCH=dedede
TEST=emerge-dedede coreboot

Change-Id: I06d8a543dbd77137cb97c4ea695a1f2b9f8ee76c
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57116
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Zanxi Chen 2021-08-24 19:19:11 +08:00 committed by Felix Held
parent 278b002348
commit 69bd94ca22
1 changed files with 9 additions and 1 deletions
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10
src/mainboard/google/dedede/variants/sasukette/overridetree.cb
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@ -99,7 +99,7 @@ chip soc/intel/jasperlake
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 52, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 52, 5000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 50, 5000),}"
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 50, 5000),}"
## Critical Policy
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
@ -118,6 +118,14 @@ chip soc/intel/jasperlake
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,}"
## Charger Performance Control (Control, mA)
register "controls.charger_perf" = "{
[0] = { 255, 3000 },
[1] = { 32, 2000 },
[2] = { 24, 1500 },
[3] = { 16, 1000 },
[4] = { 8, 500 }
}"
device generic 0 on end
end
end # SA Thermal device