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soc/amd/picasso: Allow mainboard to configure SPI settings 

This change adds options to allow mainboard to configure SPI speed for
different modes as well as the SPI read mode.

BUG=b:153675510,b:147758054
BRANCH=trembyle-bringup
TEST=Verified that SPI settings are configured correctly for trembyle.

Change-Id: I24c27ec39101c7c07bedc27056f690cf2cc54951
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40421
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh 2020-04-28 18:57:52 -07:00
parent 173c7c4594
commit 69c2811acc
2 changed files with 22 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/soc/amd/picasso/chip.h
View File

@ -10,6 +10,7 @@
#include <drivers/i2c/designware/dw_i2c.h> #include <drivers/i2c/designware/dw_i2c.h>
#include <soc/i2c.h> #include <soc/i2c.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/southbridge.h>
#include <arch/acpi_device.h> #include <arch/acpi_device.h>
struct soc_amd_picasso_config { struct soc_amd_picasso_config {
@ -70,6 +71,21 @@ struct soc_amd_picasso_config {
uint8_t core_dldo_bypass; uint8_t core_dldo_bypass;
uint8_t min_soc_vid_offset; uint8_t min_soc_vid_offset;
uint8_t aclk_dpm0_freq_400MHz; uint8_t aclk_dpm0_freq_400MHz;
/*
* SPI config
* Default values if not overridden by mainboard:
* Read mode - Normal 33MHz
* Normal speed - 66MHz
* Fast speed - 66MHz
* Alt speed - 66MHz
* TPM speed - 66MHz
*/
enum spi_read_mode spi_read_mode;
enum spi100_speed spi_normal_speed;
enum spi100_speed spi_fast_speed;
enum spi100_speed spi_altio_speed;
enum spi100_speed spi_tpm_speed;
}; };
typedef struct soc_amd_picasso_config config_t; typedef struct soc_amd_picasso_config config_t;

8
src/soc/amd/picasso/southbridge.c
View File

@ -23,6 +23,7 @@
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/nvs.h> #include <soc/nvs.h>
#include <types.h> #include <types.h>
#include "chip.h"
#define FCH_AOAC_UART_FOR_CONSOLE \ #define FCH_AOAC_UART_FOR_CONSOLE \
(CONFIG_UART_FOR_CONSOLE == 0 ? FCH_AOAC_DEV_UART0 \ (CONFIG_UART_FOR_CONSOLE == 0 ? FCH_AOAC_DEV_UART0 \
@ -237,8 +238,11 @@ void sb_read_mode(u32 mode)
static void sb_spi_config_modes(void) static void sb_spi_config_modes(void)
{ {
sb_set_spi100(SPI_SPEED_33M, SPI_SPEED_33M, const struct soc_amd_picasso_config *cfg = config_of_soc();
SPI_SPEED_16M, SPI_SPEED_16M);
sb_read_mode(cfg->spi_read_mode);
sb_set_spi100(cfg->spi_normal_speed, cfg->spi_fast_speed, cfg->spi_altio_speed,
cfg->spi_tpm_speed);
} }
static void sb_spi_init(void) static void sb_spi_init(void)