mb/google/hatch/moonbuggy: Update GPIOs
Implement the GPIOs that have been changed from genesis. - Connect scaler UART on pins C12/C13 - Connect the HDMI redriver I2C on C18/C19 - Connect the iMX8 signals on D1/D2/D3/D21/D22 - Connect the EC interrupt on D14 (same as on scout) - Connect PCH_TYPEC_UPFB on E15 (same as on genesis) - Configure as not connected the following unused pins: D23, E11, E12, F11 -> F22, H0, H8, H9 BUG=b:200876872 TEST=moonbuggy boots Change-Id: Ie9cafe81e391bce6ab7ffbe23c2d57b407d146f3 Signed-off-by: Pablo Ceballos <pceballos@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Pablo Ceballos
Felix Held
parent
77b1ff0f9d
commit
69c3611226
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@ -43,47 +43,57 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE),
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/* C10 : PCH_PCON_RST_ODL */
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PAD_CFG_GPO(GPP_C10, 1, DEEP),
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/* C11 : PCH_PCON_PDB_ODL */
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/* C11 : PCH_PCON1_PDB_ODL */
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PAD_CFG_GPO(GPP_C11, 1, DEEP),
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/* C12 : PCH_UART1_RX_ADB_TX */
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PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
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/* C13 : PCH_UART1_TX_ADB_RX */
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PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
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/* C15 : WLAN_OFF_L */
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PAD_CFG_GPO(GPP_C15, 1, DEEP),
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/* C16 : PCH_I2C_RFU_SDA (NC) */
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PAD_NC(GPP_C16, NONE),
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/* C17 : PCH_I2C_RFU_SCL (NC) */
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PAD_NC(GPP_C17, NONE),
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/* C18 : EC_I2C_HDMI_RE_SCL */
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
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/* C19 : EC_12C_HDMI_RE_SDA */
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
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/* D1 : REC_MODE */
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PAD_CFG_GPO(GPP_D1, 1, DEEP),
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/* D2 : DEV_MODE_CTRL */
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PAD_CFG_GPO(GPP_D2, 1, DEEP),
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/* D3 : BOOT_IND */
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PAD_CFG_GPI(GPP_D3, NONE, DEEP),
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/* D14 : EC_PCH_INT_L */
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PAD_CFG_GPI_APIC(GPP_D14, NONE, PLTRST, LEVEL, INVERT),
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/* D21 : BOOT_SEL_N */
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PAD_CFG_GPO(GPP_D21, 1, DEEP),
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/* D22 : QSPI_MR_N */
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PAD_CFG_GPO(GPP_D22, 1, DEEP),
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/* D23 : Not connected */
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PAD_NC(GPP_D23, NONE),
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/* E2 : Not connected */
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PAD_NC(GPP_E2, NONE),
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/* E3 : TPU_RST_PIN40 */
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/* E3 : TPU_BOOT_DELAY_PIN40 */
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PAD_CFG_GPO(GPP_E3, 1, DEEP),
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/* E7 : TPU_RST_PIN42 */
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/* E7 : TPU_BOOT_DELAY_PIN42 */
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PAD_CFG_GPO(GPP_E7, 1, DEEP),
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/* E9 : PU 10K to PP3300_SOC_A */
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PAD_NC(GPP_E9, NONE),
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/* E10 : USB_A1_OC_ODL */
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PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
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/* E11 : PU 10K to PP3300_SOC_A */
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PAD_NC(GPP_E11, NONE),
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/* E12 : PU 10K to PP3300_SOC_A */
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PAD_NC(GPP_E12, NONE),
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/* E15 : PCH_TYPEC_UPFB */
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PAD_CFG_GPI(GPP_E15, NONE, DEEP),
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/* F11 : EMMC_CMD */
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PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
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/* F12 : EMMC_DATA0 */
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PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
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/* F13 : EMMC_DATA1 */
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PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
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/* F14 : EMMC_DATA2 */
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PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
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/* F15 : EMMC_DATA3 */
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PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
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/* F16 : EMMC_DATA4 */
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PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
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/* F17 : EMMC_DATA5 */
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PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
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/* F18 : EMMC_DATA6 */
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PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
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/* F19 : EMMC_DATA7 */
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
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/* F20 : EMMC_RCLK */
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
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/* F21 : EMMC_CLK */
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
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/* F22 : EMMC_RST_L */
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PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
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/* H0 : Not connected */
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PAD_NC(GPP_H0, NONE),
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/* H4 : PCH_I2C_PCON_SDA */
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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/* H5 : PCH_I2C_PCON_SCL */
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@ -92,6 +102,10 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : PCH_I2C_TPU_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/* H8 : Not connected */
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PAD_NC(GPP_H8, NONE),
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/* H9 : Not connected */
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PAD_NC(GPP_H9, NONE),
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/* H22 : PWM_PP3300_BIOZZER */
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PAD_CFG_GPO(GPP_H22, 0, DEEP),
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};
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@ -122,7 +136,7 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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/* C20 : PCH_WP_OD */
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PAD_CFG_GPI(GPP_C20, NONE, DEEP),
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/* C21 : H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
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@ -5,4 +5,7 @@
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#include <baseboard/gpio.h>
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#undef EC_SYNC_IRQ
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#define EC_SYNC_IRQ GPP_D14_IRQ
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#endif
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@ -13,7 +13,7 @@ chip soc/intel/cannonlake
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[PchSerialIoIndexSPI1] = PchSerialIoPci,
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[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART1] = PchSerialIoPci,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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@ -451,6 +451,8 @@ chip soc/intel/cannonlake
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device pci 1d.5 on end # PCI Root Port 14 (non-root)
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device pci 1d.6 on end # PCI Root Port 15 (non-root)
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device pci 1d.7 on end # PCI Root Port 16 (non-root)
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device pci 1e.0 on end # UART #0
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device pci 1e.1 on end # UART #1
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device pci 1e.3 off end # GSPI #1
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end
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