mb/*: Remove lapic from devicetree
The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans
parent
0a97e46616
commit
69cd729c0c
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@ -100,9 +100,7 @@ chip soc/intel/skylake
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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@ -32,9 +32,7 @@ chip soc/intel/skylake
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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subsystemid 0x1025 0x1037 inherit
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device ref system_agent on
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@ -41,9 +41,7 @@ chip soc/intel/skylake
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on # Host Bridge
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subsystemid 0x1849 0x191f
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@ -1,9 +1,5 @@
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chip northbridge/intel/i440bx # Northbridge
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device cpu_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device lapic 0 on end # APIC
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end
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end
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device cpu_cluster 0 on end # APIC cluster
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device domain 0 on # PCI domain
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device pci 0.0 on end # Host bridge
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device pci 1.0 on end # PCI/AGP bridge
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@ -1,11 +1,5 @@
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chip northbridge/intel/i440bx # Northbridge
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device cpu_cluster 0 on # (L)APIC cluster
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chip cpu/intel/slot_1 # CPU socket 0
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device lapic 0 on end # Local APIC of CPU 0
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end
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chip cpu/intel/slot_1 # CPU socket 1
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device lapic 1 on end # Local APIC of CPU 1
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end
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end
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device domain 0 on # PCI domain
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chip southbridge/intel/i82371eb # Southbridge
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@ -1,11 +1,5 @@
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chip northbridge/intel/i440bx # Northbridge
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device cpu_cluster 0 on # (L)APIC cluster
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chip cpu/intel/slot_1 # CPU socket 0
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device lapic 0 on end # Local APIC of CPU 0
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end
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chip cpu/intel/slot_1 # CPU socket 1
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device lapic 1 on end # Local APIC of CPU 1
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end
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end
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device domain 0 on # PCI domain
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chip southbridge/intel/i82371eb # Southbridge
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@ -29,9 +29,7 @@ chip soc/intel/baytrail
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# Disable SLP_X stretching after SUS power well fail.
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register "disable_slp_x_stretch_sus_fail" = "1"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # SoC router
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device pci 02.0 on end # GFX
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@ -55,9 +55,7 @@ chip soc/intel/cannonlake
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register "gpe0_dw2" = "PMC_GPP_E"
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# Actual device tree
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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subsystemid 0x1558 0x1401 inherit
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@ -35,9 +35,7 @@ chip soc/intel/skylake
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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subsystemid 0x1558 0x1313 inherit
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device ref system_agent on end
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@ -2,7 +2,6 @@ chip soc/intel/tigerlake
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device cpu_cluster 0 on
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register "tcc_offset" = "12"
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register "eist_enable" = "true"
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device lapic 0 on end
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end
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device domain 0 on
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subsystemid 0x1558 0x14a1 inherit
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@ -1,9 +1,5 @@
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chip mainboard/emulation/qemu-i440fx
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device cpu_cluster 0 on
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chip cpu/qemu-x86
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 0.0 on end # northbridge (i440fx)
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chip southbridge/intel/i82371eb # southbridge
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@ -1,9 +1,5 @@
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chip mainboard/emulation/qemu-q35
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device cpu_cluster 0 on
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chip cpu/qemu-x86
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 0.0 mandatory end # northbridge (q35)
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chip southbridge/intel/i82801ix
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@ -82,9 +82,7 @@ chip soc/intel/braswell
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# CPLD requires continuous mode
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # 8086 2280 - SoC router
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@ -212,9 +212,7 @@ chip soc/intel/skylake
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[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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@ -5,11 +5,7 @@ chip northbridge/intel/pineview # Northbridge
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register "use_crt" = "true"
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register "use_lvds" = "false"
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device cpu_cluster 0 on # APIC cluster
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chip cpu/intel/socket_FCBGA559 # CPU
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device lapic 0 on end # APIC
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end
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end
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device cpu_cluster 0 on end # APIC cluster
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device domain 0 on # PCI domain
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subsystemid 0x105b 0x0d55 inherit
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device pci 0.0 on end # Host Bridge
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@ -2,11 +2,7 @@
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chip northbridge/intel/i945
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device cpu_cluster 0 on
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ops i945_cpu_bus_ops
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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device cpu_cluster 0 on ops i945_cpu_bus_ops
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end
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register "pci_mmio_size" = "768"
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@ -3,11 +3,7 @@
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chip northbridge/intel/pineview
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register "use_crt" = "true"
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device cpu_cluster 0 on
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chip cpu/intel/socket_FCBGA559
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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subsystemid 0x105b 0x0d55 inherit
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device pci 0.0 on end # Host Bridge
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@ -91,9 +91,7 @@ chip soc/intel/braswell
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# Allow PCIe devices to wake system from suspend
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register "pcie_wake_enable" = "1"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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# EDS Table 24-4, Figure 24-5
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device pci 00.0 on end # 8086 2280 - SoC transaction router
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@ -216,9 +216,7 @@ chip soc/intel/cannonlake
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on
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@ -228,9 +228,7 @@ chip soc/intel/skylake
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}"
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register "tcc_offset" = "10"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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@ -305,9 +305,7 @@ chip soc/intel/skylake
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}"
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register "tcc_offset" = "6" # TCC of 94C
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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@ -81,9 +81,7 @@ chip soc/intel/skylake
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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@ -195,9 +195,7 @@ chip soc/intel/cannonlake
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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@ -1,7 +1,5 @@
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chip soc/intel/apollolake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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register "pcie_rp_clkreq_pin[2]" = "3" # wifi/bt
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# Disable unused clkreq of PCIe root ports
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@ -227,9 +227,7 @@ chip soc/intel/skylake
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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@ -249,9 +249,7 @@ chip soc/intel/skylake
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# Use default SD card detect GPIO configuration
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register "sdcard_cd_gpio" = "GPP_E15"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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@ -264,9 +264,7 @@ chip soc/intel/skylake
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.psys_pmax = 101,
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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@ -271,9 +271,7 @@ chip soc/intel/skylake
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# Use default SD card detect GPIO configuration
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register "sdcard_cd_gpio" = "GPP_E15"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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@ -244,9 +244,7 @@ chip soc/intel/skylake
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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@ -230,9 +230,7 @@ chip soc/intel/skylake
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# Use default SD card detect GPIO configuration
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register "sdcard_cd_gpio" = "GPP_E15"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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@ -250,9 +250,7 @@ chip soc/intel/skylake
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# Use default SD card detect GPIO configuration
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register "sdcard_cd_gpio" = "GPP_E15"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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@ -195,9 +195,7 @@ chip soc/intel/cannonlake
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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@ -53,9 +53,7 @@ chip soc/intel/baytrail
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# Disable SLP_X stretching after SUS power well fail.
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register "disable_slp_x_stretch_sus_fail" = "1"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # SoC router
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device pci 02.0 on end # GFX
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@ -1,8 +1,6 @@
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chip soc/intel/apollolake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
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# Disable unused clkreq of PCIe root ports
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@ -1,8 +1,6 @@
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chip soc/intel/apollolake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
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# Disable unused clkreq of PCIe root ports
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@ -1,8 +1,6 @@
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chip soc/intel/apollolake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
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# Disable unused clkreq of PCIe root ports
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@ -1,8 +1,6 @@
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chip soc/intel/apollolake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
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# Disable unused clkreq of PCIe root ports
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@ -1,8 +1,6 @@
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chip soc/intel/apollolake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
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# Disable unused clkreq of PCIe root ports
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@ -208,9 +208,7 @@ chip soc/intel/cannonlake
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register "gpio_pm[COMM_3]" = "MISCCFG_GPIO_PM_CONFIG_BITS"
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register "gpio_pm[COMM_4]" = "MISCCFG_GPIO_PM_CONFIG_BITS"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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@ -213,9 +213,7 @@ chip soc/intel/cannonlake
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register "gpio_pm[COMM_3]" = "MISCCFG_GPIO_PM_CONFIG_BITS"
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register "gpio_pm[COMM_4]" = "MISCCFG_GPIO_PM_CONFIG_BITS"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
|
|
|
|||
|
|
@ -1,8 +1,7 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/nvidia/tegra210
|
||||
device cpu_cluster 0 on
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
register "display_controller" = "TEGRA_ARM_DISPLAYA"
|
||||
register "xres" = "2560"
|
||||
|
|
|
|||
|
|
@ -7,9 +7,7 @@ chip soc/intel/skylake
|
|||
|
||||
register "eist_enable" = "1"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
device domain 0 on
|
||||
subsystemid 0x103c 0x2b5e inherit
|
||||
device pci 00.0 on end # Host bridge
|
||||
|
|
|
|||
|
|
@ -6,9 +6,7 @@ fw_config
|
|||
end
|
||||
chip soc/intel/alderlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
|
|
|
|||
|
|
@ -7,9 +7,7 @@ chip soc/intel/apollolake
|
|||
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # - Host Bridge
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/xeon_sp/cpx
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host bridge
|
||||
device pci 04.0 on end
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/cannonlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
# FSP configuration
|
||||
register "SaGv" = "SaGv_Enabled"
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/cannonlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
# FSP configuration
|
||||
register "RMT" = "1"
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/cannonlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
# FSP configuration
|
||||
register "RMT" = "1"
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/cannonlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
register "PchHdaDspEnable" = "1"
|
||||
register "PchHdaAudioLinkHda" = "1"
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/cannonlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
# Enable eDP device
|
||||
register "DdiPortEdp" = "1"
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/cannonlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
# Enable eDP device
|
||||
register "DdiPortEdp" = "1"
|
||||
|
|
|
|||
|
|
@ -5,11 +5,7 @@ chip northbridge/intel/pineview # Northbridge
|
|||
register "use_crt" = "true"
|
||||
register "use_lvds" = "false"
|
||||
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/socket_FCBGA559 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device cpu_cluster 0 on end # APIC cluster
|
||||
device domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host Bridge
|
||||
device pci 2.0 on end # Integrated graphics controller
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/elkhartlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/apollolake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
|
||||
# Disable unused clkreq of PCIe root ports
|
||||
|
|
|
|||
|
|
@ -109,9 +109,7 @@ chip soc/intel/skylake
|
|||
# Send an extra VR mailbox command for the PS4 exit issue
|
||||
register "SendVrMbxCmd" = "2"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
|
|
|
|||
|
|
@ -150,9 +150,7 @@ chip soc/intel/skylake
|
|||
# Use default SD card detect GPIO configuration
|
||||
register "sdcard_cd_gpio" = "GPP_G5"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
device domain 0 on
|
||||
device pci 15.2 off end # I2C #2
|
||||
device pci 15.3 off end # I2C #3
|
||||
|
|
|
|||
|
|
@ -157,9 +157,7 @@ chip soc/intel/skylake
|
|||
# Use default SD card detect GPIO configuration
|
||||
register "sdcard_cd_gpio" = "GPP_A7"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
|
|
|
|||
|
|
@ -7,9 +7,7 @@ chip soc/intel/apollolake
|
|||
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # - Host Bridge
|
||||
|
|
|
|||
|
|
@ -7,9 +7,7 @@ chip soc/intel/apollolake
|
|||
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # - Host Bridge
|
||||
|
|
|
|||
|
|
@ -192,9 +192,7 @@ chip soc/intel/skylake
|
|||
# Use default SD card detect GPIO configuration
|
||||
#register "sdcard_cd_gpio" = "GPP_A7"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/alderlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
|
|
|
|||
|
|
@ -80,9 +80,7 @@ chip soc/intel/braswell
|
|||
# Allow PCIe devices to wake system from suspend
|
||||
register "pcie_wake_enable" = "1"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
device domain 0 on
|
||||
# EDS Table 24-4, Figure 24-5
|
||||
device pci 00.0 on end # 8086 2280 - SoC transaction router
|
||||
|
|
|
|||
|
|
@ -63,9 +63,7 @@ chip soc/intel/skylake
|
|||
# Send an extra VR mailbox command for the PS4 exit issue
|
||||
register "SendVrMbxCmd" = "2"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
|
|
|
|||
|
|
@ -2,9 +2,7 @@
|
|||
|
||||
chip soc/intel/apollolake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
# Override USB port configuration
|
||||
register "usb_config_override" = "1"
|
||||
|
|
|
|||
|
|
@ -5,9 +5,7 @@ chip soc/intel/apollolake
|
|||
register "enable_vtd" = "1"
|
||||
register "dptf_enable" = "1"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 00.1 on end # DPTF
|
||||
|
|
|
|||
|
|
@ -152,9 +152,7 @@ chip soc/intel/skylake
|
|||
# Send an extra VR mailbox command for the PS4 exit issue
|
||||
register "SendVrMbxCmd" = "2"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
|
|
|
|||
|
|
@ -48,9 +48,7 @@ chip soc/intel/xeon_sp/cpx
|
|||
|
||||
register "cstate_states" = "CSTATES_C1C6"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device gpio 0 alias pch_gpio on end
|
||||
|
|
|
|||
|
|
@ -40,9 +40,7 @@ chip soc/intel/xeon_sp/skx
|
|||
|
||||
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device gpio 0 alias pch_gpio on end
|
||||
|
|
|
|||
|
|
@ -1,11 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip northbridge/amd/pi/00730F01/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/pi/00730F01
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x1410 inherit
|
||||
|
|
|
|||
|
|
@ -1,11 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip northbridge/amd/pi/00730F01/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/pi/00730F01
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x1410 inherit
|
||||
|
|
|
|||
|
|
@ -1,11 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip northbridge/amd/pi/00730F01/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/pi/00730F01
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x1410 inherit
|
||||
|
|
|
|||
|
|
@ -1,11 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip northbridge/amd/pi/00730F01/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/pi/00730F01
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x1410 inherit
|
||||
|
|
|
|||
|
|
@ -79,9 +79,7 @@ chip soc/intel/braswell
|
|||
# Allow PCIe devices to wake system from suspend
|
||||
register "pcie_wake_enable" = "1"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # 8086 2280 - SoC router
|
||||
|
|
|
|||
|
|
@ -136,9 +136,7 @@ chip soc/intel/cannonlake
|
|||
|
||||
register "DisableHeciRetry" = "1"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
|
|
|
|||
|
|
@ -79,9 +79,7 @@ chip soc/intel/braswell
|
|||
# Enable SERIRQ continuous
|
||||
register "serirq_mode" = "SERIRQ_CONTINUOUS"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # 8086 2280 - SoC transaction router
|
||||
device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping GFX
|
||||
|
|
|
|||
|
|
@ -189,9 +189,7 @@ chip soc/intel/skylake
|
|||
[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
|
||||
}"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
|
|
|
|||
|
|
@ -41,9 +41,7 @@ chip soc/intel/cannonlake
|
|||
register "gpe0_dw2" = "PMC_GPP_E"
|
||||
|
||||
# Actual device tree
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
|
|
|
|||
|
|
@ -149,9 +149,7 @@ chip soc/intel/skylake
|
|||
# Send an extra VR mailbox command for the PS4 exit issue
|
||||
register "SendVrMbxCmd" = "2"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
|
|
|
|||
|
|
@ -166,9 +166,7 @@ chip soc/intel/skylake
|
|||
[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
|
||||
}"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
|
|
|
|||
|
|
@ -31,9 +31,7 @@ chip soc/intel/denverton_ns
|
|||
register "ipc2" = "0x00000000" # IPC2
|
||||
register "ipc3" = "0x00000000" # IPC3
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
|
|
|
|||
|
|
@ -7,9 +7,7 @@ chip soc/intel/cannonlake
|
|||
register "PchHdaDspEnable" = "0"
|
||||
register "PchHdaAudioLinkHda" = "1"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
|
|
|
|||
|
|
@ -7,9 +7,7 @@ chip soc/intel/cannonlake
|
|||
register "PchHdaDspEnable" = "0"
|
||||
register "PchHdaAudioLinkHda" = "1"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/apollolake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
register "sci_irq" = "SCIS_IRQ10"
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/apollolake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
register "sci_irq" = "SCIS_IRQ10"
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/apollolake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
register "sci_irq" = "SCIS_IRQ10"
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/apollolake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
register "sci_irq" = "SCIS_IRQ10"
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/apollolake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
register "sci_irq" = "SCIS_IRQ10"
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/apollolake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
register "sci_irq" = "SCIS_IRQ10"
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/apollolake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
register "sci_irq" = "SCIS_IRQ10"
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/elkhartlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/elkhartlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
chip soc/intel/elkhartlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
chip soc/intel/apollolake
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
# Graphics
|
||||
# TODO:
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
chip soc/intel/apollolake
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
# Graphics
|
||||
# TODO:
|
||||
|
|
|
|||
|
|
@ -38,9 +38,7 @@ chip soc/intel/alderlake
|
|||
register "pmc_gpe0_dw2" = "GPP_E"
|
||||
|
||||
# Device Tree
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device ref igpu on
|
||||
|
|
|
|||
|
|
@ -50,9 +50,7 @@ chip soc/intel/cannonlake
|
|||
register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
|
||||
|
||||
# Actual device tree.
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
|
|
|
|||
|
|
@ -49,9 +49,7 @@ chip soc/intel/skylake
|
|||
LPC_IOE_EC_62_66"
|
||||
|
||||
# Actual device tree.
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device ref igpu on end
|
||||
|
|
|
|||
|
|
@ -64,9 +64,7 @@ chip soc/intel/tigerlake
|
|||
register "PcieClkSrcClkReq[6]" = "PCIE_CLK_NOTUSED"
|
||||
|
||||
# Actual device tree.
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device ref igpu on end
|
||||
|
|
|
|||
|
|
@ -26,9 +26,7 @@ chip soc/intel/skylake
|
|||
register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
|
||||
register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 01.0 off end # CPU PCIe Port 10 (x16)
|
||||
|
|
|
|||
|
|
@ -47,9 +47,7 @@ chip soc/intel/cannonlake
|
|||
register "gpe0_dw2" = "PMC_GPP_E"
|
||||
|
||||
# Actual device tree
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x65d1 inherit
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue