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northbridge/intel/haswell: Add space around operators 

Change-Id: I8fa1e39bfd950475e3b55d6debcbfd92615aa379
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16628
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2016-09-17 20:32:07 +02:00 committed by Patrick Georgi
parent f352e2fab8
commit 69d658f59d
3 changed files with 4 additions and 4 deletions
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2
src/northbridge/intel/haswell/acpi.c
View File

@ -39,7 +39,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
if (!dev)
return current;
pciexbar_reg=pci_read_config32(dev, PCIEXBAR);
pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
// MMCFG not supported or not enabled.
if (!(pciexbar_reg & (1 << 0)))

2
src/northbridge/intel/haswell/acpi/hostbridge.asl
View File

@ -144,7 +144,7 @@ Device (MCHC)
}
/*
* Search CPU0 _PSS looking for control=arg0 and then
* Search CPU0 _PSS looking for control = arg0 and then
* return previous P-state entry number for new _PPC
*
* Format of _PSS:

4
src/northbridge/intel/haswell/gma.c
View File

@ -98,7 +98,7 @@ static const struct gt_reg haswell_gt_lock[] = {
u32 map_oprom_vendev(u32 vendev)
{
u32 new_vendev=vendev;
u32 new_vendev = vendev;
switch (vendev) {
case 0x80860402: /* GT1 Desktop */
@ -116,7 +116,7 @@ u32 map_oprom_vendev(u32 vendev)
case 0x8086042a: /* GT3 Server */
case 0x80860a26: /* GT3 ULT */
new_vendev=0x80860406; /* GT1 Mobile */
new_vendev = 0x80860406; /* GT1 Mobile */
break;
}