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mb/google/nissa/var/pirrha: Update device configurations 

Based on schematics and gpio table of pirrha, generate overridetree.cb
to configure internal devices and generate fw_config.c to override
GPIO configurations following FW_CONFIG.

BUG=b:292134655
TEST=FW_NAME=pirrha emerge-nissa coreboot chromeos-bootimage

Change-Id: I91013b0ad89e26f0a4c433c305c6b883d000f042
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77116
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jimmy Su <jimmy.su@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
This commit is contained in:
Seunghwan Kim 2023-08-10 10:27:18 +09:00 committed by Felix Held
parent 820a31263d
commit 69f0289608
3 changed files with 615 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/brya/variants/pirrha/Makefile.inc
View File

@ -3,4 +3,5 @@ bootblock-y += gpio.c
romstage-y += memory.c
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
ramstage-y += gpio.c

81
src/mainboard/google/brya/variants/pirrha/fw_config.c Normal file
View File

@ -0,0 +1,81 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <boardid.h>
#include <console/console.h>
#include <fw_config.h>
static const struct pad_config wfc_disable_pads[] = {
/* D3 : WCAM_RST_L */
PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
/* D15 : EN_PP2800_WCAM_X */
PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
/* D16 : EN_PP1800_PP1200_WCAM_X */
PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
/* H22 : WCAM_MCLK_R */
PAD_NC(GPP_H22, NONE),
/* R6 : DMIC_WCAM_CLK_R */
PAD_NC(GPP_R6, NONE),
/* R7 : DMIC_WCAM_DATA */
PAD_NC(GPP_R7, NONE),
};
static const struct pad_config emmc_disable_pads[] = {
/* I7 : EMMC_CMD */
PAD_NC(GPP_I7, NONE),
/* I8 : EMMC_D0 */
PAD_NC(GPP_I8, NONE),
/* I9 : EMMC_D1 */
PAD_NC(GPP_I9, NONE),
/* I10 : EMMC_D2 */
PAD_NC(GPP_I10, NONE),
/* I11 : EMMC_D3 */
PAD_NC(GPP_I11, NONE),
/* I12 : EMMC_D4 */
PAD_NC(GPP_I12, NONE),
/* I13 : EMMC_D5 */
PAD_NC(GPP_I13, NONE),
/* I14 : EMMC_D6 */
PAD_NC(GPP_I14, NONE),
/* I15 : EMMC_D7 */
PAD_NC(GPP_I15, NONE),
/* I16 : EMMC_RCLK */
PAD_NC(GPP_I16, NONE),
/* I17 : EMMC_CLK */
PAD_NC(GPP_I17, NONE),
/* I18 : EMMC_RST_L */
PAD_NC(GPP_I18, NONE),
};
static const struct pad_config stylus_disable_pads[] = {
/* F13 : SOC_PEN_DETECT_R_ODL */
PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
/* F15 : SOC_PEN_DETECT_ODL */
PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
};
void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
{
// Skip checking FW config if board ID in CBI is not verified.
if (board_id() == BOARD_ID_UNKNOWN)
return;
if (fw_config_probe(FW_CONFIG(WFC, WFC_ABSENT))) {
printk(BIOS_INFO, "Disable MIPI WFC GPIO pins.\n");
gpio_padbased_override(padbased_table, wfc_disable_pads,
ARRAY_SIZE(wfc_disable_pads));
}
if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) {
printk(BIOS_INFO, "Disable eMMC SSD GPIO pins.\n");
gpio_padbased_override(padbased_table, emmc_disable_pads,
ARRAY_SIZE(emmc_disable_pads));
}
if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) {
printk(BIOS_INFO, "Disable Stylus GPIO pins.\n");
gpio_padbased_override(padbased_table, stylus_disable_pads,
ARRAY_SIZE(stylus_disable_pads));
}
}

538
src/mainboard/google/brya/variants/pirrha/overridetree.cb
View File

@ -1,6 +1,534 @@
chip soc/intel/alderlake
device domain 0 on
end
fw_config
field DB_USB 0 1
option DB_NONE 0
option DB_1C_1A 1
option DB_1C_LTE 2
end
field WFC 2
option WFC_MIPI_OV8856 0
option WFC_ABSENT 1
end
field STYLUS 3
option STYLUS_PRESENT 0
option STYLUS_ABSENT 1
end
end
chip soc/intel/alderlake
# GPE configuration
register "pmc_gpe0_dw1" = "GPP_C"
# Enable MIPI DSI on DDI port A
register "ddi_portA_config" = "2" # MIPI DSI
register "sagv" = "SaGv_Enabled"
# SOC Aux orientation override:
# This is a bitfield that corresponds to up to 4 TCSS ports.
# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
# TcssAuxOri = 0101b
# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
# motherboard to USBC connector
register "tcss_aux_ori" = "5"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
register "usb2_ports[0]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.pre_emp_bias = USB2_BIAS_28P15MV,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
.type_c = 1,
}" # USB2_C0
register "usb2_ports[1]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.pre_emp_bias = USB2_BIAS_28P15MV,
.tx_bias = USB2_BIAS_11P25MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
.type_c = 1,
}" # USB2_C1
register "usb2_ports[3]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.pre_emp_bias = USB2_BIAS_28P15MV,
.tx_bias = USB2_BIAS_11P25MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
}" # USB2_A0
register "usb2_ports[4]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.pre_emp_bias = USB2_BIAS_28P15MV,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON,
.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
}" # uSD
register "usb2_ports[5]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
}" # UFCamera
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
}"
# Configure external V1P05/Vnn/VnnSx Rails
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX ,
.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX ,
.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_RETENTION,
.v1p05_voltage_mv = 1050,
.vnn_voltage_mv = 780,
.vnn_sx_voltage_mv = 1050,
.v1p05_icc_max_ma = 500,
.vnn_icc_max_ma = 500,
}"
# VR Settings
register "domain_vr_config[VR_DOMAIN_IA]" = "{
.vr_config_enable = 1,
.tdc_timewindow = 1000,
.ac_loadline = 500,
.dc_loadline = 500,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
}"
register "domain_vr_config[VR_DOMAIN_GT]" = "{
.vr_config_enable = 1,
.tdc_timewindow = 1000,
.psi1threshold = VR_CFG_AMP(13),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
}"
# Enable the Cnvi BT Audio Offload
register "cnvi_bt_audio_offload" = "1"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| I2C1 | Touchscreen |
#| I2C2 | WCAM |
#| I2C3 | Audio |
#| I2C4 | EMR |
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.panel_orientation = LB_FB_ORIENTATION_RIGHT_UP,
.i2c[0] = {
.early_init = 1,
.speed = I2C_SPEED_FAST_PLUS,
.speed_config[0] = {
.speed = I2C_SPEED_FAST_PLUS,
.scl_lcnt = 55,
.scl_hcnt = 30,
.sda_hold = 7,
}
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 157,
.scl_hcnt = 79,
.sda_hold = 7,
}
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 157,
.scl_hcnt = 79,
.sda_hold = 7,
}
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 158,
.scl_hcnt = 79,
.sda_hold = 7,
}
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 158,
.scl_hcnt = 79,
.sda_hold = 7,
}
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 158,
.scl_hcnt = 79,
.sda_hold = 7,
}
},
}"
device domain 0 on
device ref dtt on
chip drivers/intel/dptf
## sensor information
register "options.tsr[0].desc" = ""Memory""
register "options.tsr[1].desc" = ""Charger""
register "options.tsr[2].desc" = ""Ambient""
# TODO: below values are initial reference values only
## Passive Policy
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
}"
## Critical Policy
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
}"
register "controls.power_limits" = "{
.pl1 = {
.min_power = 3000,
.max_power = 6000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200
},
.pl2 = {
.min_power = 25000,
.max_power = 25000,
.time_window_min = 1,
.time_window_max = 1,
.granularity = 1000
}
}"
## Charger Performance Control (Control, mA)
register "controls.charger_perf" = "{
[0] = { 255, 1700 },
[1] = { 24, 1500 },
[2] = { 16, 1000 },
[3] = { 8, 500 }
}"
device generic 0 on end
end
end
device ref ipu on
chip drivers/intel/mipi_camera
register "acpi_uid" = "0x50000"
register "acpi_name" = ""IPU0""
register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
register "cio2_num_ports" = "1"
register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used
register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0""
register "cio2_prt[0]" = "2"
device generic 0 on
probe WFC WFC_MIPI_OV8856
end
end
end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "enable_cnvi_ddr_rfim" = "true"
device generic 0 on end
end
end
device ref i2c1 on
chip drivers/i2c/hid
register "generic.hid" = ""HX121A""
register "generic.desc" = ""HX Touchscreen""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
register "generic.probed" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
register "generic.reset_delay_ms" = "200"
register "generic.reset_off_delay_ms" = "2"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x1"
device i2c 0x4F on end
end
end
device ref i2c2 on
chip drivers/intel/mipi_camera
register "acpi_hid" = ""OVTI8856""
register "acpi_uid" = "0"
register "acpi_name" = ""CAM0""
register "chip_name" = ""Ov 8856 Camera""
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
register "ssdb.lanes_used" = "4"
register "ssdb.link_used" = "1"
register "ssdb.vcm_type" = "0x0C"
register "vcm_name" = ""VCM0""
register "num_freq_entries" = "2"
register "link_freq[0]" = "360000000"
register "link_freq[1]" = "180000000"
register "remote_name" = ""IPU0""
register "has_power_resource" = "1"
#Controls
register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X
register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X
register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L
#_ON
register "on_seq.ops_cnt" = "5"
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
#_OFF
register "off_seq.ops_cnt" = "4"
register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
device i2c 36 on
probe WFC WFC_MIPI_OV8856
end
end
chip drivers/intel/mipi_camera
register "acpi_uid" = "3"
register "acpi_name" = ""VCM0""
register "chip_name" = ""DW AF DAC""
register "device_type" = "INTEL_ACPI_CAMERA_VCM"
register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC""
register "vcm_compat" = ""dongwoon,dw9714""
device i2c 0C on
probe WFC WFC_MIPI_OV8856
end
end
chip drivers/intel/mipi_camera
register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
register "acpi_uid" = "1"
register "acpi_name" = ""NVM0""
register "chip_name" = ""GT24C08""
register "device_type" = "INTEL_ACPI_CAMERA_NVM"
register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC""
register "nvm_size" = "0x2000"
register "nvm_pagesize" = "1"
register "nvm_readonly" = "1"
register "nvm_width" = "0x10"
register "nvm_compat" = ""atmel,24c08""
device i2c 50 on
probe WFC WFC_MIPI_OV8856
end
end
end
device ref i2c3 on
chip drivers/i2c/da7219
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
register "btn_cfg" = "50"
register "mic_det_thr" = "500"
register "jack_ins_deb" = "20"
register "jack_det_rate" = ""32ms_64ms""
register "jack_rem_deb" = "1"
register "a_d_btn_thr" = "0xa"
register "d_b_btn_thr" = "0x16"
register "b_c_btn_thr" = "0x21"
register "c_mic_btn_thr" = "0x3e"
register "btn_avg" = "4"
register "adc_1bit_rpt" = "1"
register "micbias_lvl" = "2600"
register "mic_amp_in_sel" = ""diff""
device i2c 1a on end
end
end
device ref i2c4 on
chip drivers/i2c/hid
register "generic.hid" = ""WCOM014B""
register "generic.desc" = ""WCOM Digitizer""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F12_IRQ)"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
register "generic.enable_delay_ms" = "20"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
register "generic.reset_delay_ms" = "100"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x1"
device i2c 0x09 on
probe STYLUS STYLUS_PRESENT
end
end
end
device ref i2c5 on
chip drivers/i2c/hid
register "generic.hid" = ""ZNT0000""
register "generic.desc" = ""Zinitix Touchpad""
register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
register "generic.wake" = "GPE0_DW2_14"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0xE"
device i2c 40 on end
end
end
device ref hda on
chip drivers/generic/max98357a
register "hid" = ""MX98360A""
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
register "sdmode_delay" = "5"
device generic 0 on end
end
end
device ref pcie_rp7 off end
device ref pcie_rp9 off end
device ref emmc on
probe STORAGE STORAGE_EMMC
end
device ref ish on
chip drivers/intel/ish
register "add_acpi_dma_property" = "true"
device generic 0 on end
end
end
device ref ufs on
probe STORAGE STORAGE_UFS
end
device ref pch_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]
use conn1 as mux_conn[1]
device pnp 0c09.0 on end
end
end
device ref pmc hidden
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
use usb2_port1 as usb2_port
use tcss_usb3_port1 as usb3_port
device generic 0 alias conn0 on end
end
chip drivers/intel/pmc_mux/conn
use usb2_port2 as usb2_port
use tcss_usb3_port2 as usb3_port
device generic 1 alias conn1 on end
end
end
end
end
device ref tcss_xhci on
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref tcss_usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
device ref tcss_usb3_port2 on end
end
end
end
end
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A1 (DB)""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
device ref usb2_port4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 SDCard""
register "type" = "UPC_TYPE_EXPRESSCARD"
device ref usb2_port5 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Camera""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port6 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
device ref usb2_port10 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A1 (DB)""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
device ref usb3_port2 on end
end
end
end
end
end
end