AGESA boards: Use acpi_is_wakeup_s3()
Change-Id: Ib76ec433710b3a7c26360329a9403585d6f4fe4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6143 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
parent
db8693bde7
commit
6a089e3b18
|
@ -35,15 +35,9 @@
|
|||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
|
||||
/*
|
||||
* The mainboard is the first place that we get control in ramstage. Check
|
||||
* for S3 resume and call the appropriate AGESA/CIMx resume functions.
|
||||
*/
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
acpi_slp_type = acpi_get_sleep_type();
|
||||
if (acpi_slp_type == 3)
|
||||
|
||||
if (acpi_is_wakeup_s3())
|
||||
agesawrapper_fchs3earlyrestore();
|
||||
#endif
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
|
|
|
@ -35,15 +35,9 @@
|
|||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
|
||||
/*
|
||||
* The mainboard is the first place that we get control in ramstage. Check
|
||||
* for S3 resume and call the appropriate AGESA/CIMx resume functions.
|
||||
*/
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
acpi_slp_type = acpi_get_sleep_type();
|
||||
if (acpi_slp_type == 3)
|
||||
|
||||
if (acpi_is_wakeup_s3())
|
||||
agesawrapper_fchs3earlyrestore();
|
||||
#endif
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
|
|
|
@ -155,14 +155,6 @@ static void mainboard_enable(device_t dev)
|
|||
{
|
||||
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
|
||||
|
||||
/*
|
||||
* The mainboard is the first place that we get control in ramstage. Check
|
||||
* for S3 resume and call the appropriate AGESA/CIMx resume functions.
|
||||
*/
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
acpi_slp_type = acpi_get_sleep_type();
|
||||
#endif
|
||||
|
||||
/* enable GPP CLK0 thru CLK1 */
|
||||
/* disable GPP CLK2 thru SLT_GFX_CLK */
|
||||
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
|
||||
|
|
|
@ -51,16 +51,8 @@ static void mainboard_enable(device_t dev)
|
|||
msr.lo &= ~(1 << 23);
|
||||
wrmsr(0xC0011023, msr);
|
||||
|
||||
/*
|
||||
* The mainboard is the first place that we get control in ramstage. Check
|
||||
* for S3 resume and call the appropriate AGESA/CIMx resume functions.
|
||||
*/
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
acpi_slp_type = acpi_get_sleep_type();
|
||||
if (acpi_slp_type == 3)
|
||||
if (acpi_is_wakeup_s3())
|
||||
agesawrapper_fchs3earlyrestore();
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
|
|
|
@ -35,15 +35,9 @@
|
|||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
|
||||
/*
|
||||
* The mainboard is the first place that we get control in ramstage. Check
|
||||
* for S3 resume and call the appropriate AGESA/CIMx resume functions.
|
||||
*/
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
acpi_slp_type = acpi_get_sleep_type();
|
||||
if (acpi_slp_type == 3)
|
||||
|
||||
if (acpi_is_wakeup_s3())
|
||||
agesawrapper_fchs3earlyrestore();
|
||||
#endif
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
|
|
|
@ -51,16 +51,8 @@ static void mainboard_enable(device_t dev)
|
|||
msr.lo &= ~(1 << 23);
|
||||
wrmsr(0xC0011023, msr);
|
||||
|
||||
/*
|
||||
* The mainboard is the first place that we get control in ramstage. Check
|
||||
* for S3 resume and call the appropriate AGESA/CIMx resume functions.
|
||||
*/
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
acpi_slp_type = acpi_get_sleep_type();
|
||||
if (acpi_slp_type == 3)
|
||||
if (acpi_is_wakeup_s3())
|
||||
agesawrapper_fchs3earlyrestore();
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
|
|
|
@ -59,14 +59,6 @@ static void mainboard_enable(device_t dev)
|
|||
{
|
||||
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
|
||||
|
||||
/*
|
||||
* The mainboard is the first place that we get control in ramstage. Check
|
||||
* for S3 resume and call the appropriate AGESA/CIMx resume functions.
|
||||
*/
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
acpi_slp_type = acpi_get_sleep_type();
|
||||
#endif
|
||||
|
||||
/* enable GPP CLK0 thru CLK1 */
|
||||
/* disable GPP CLK2 thru SLT_GFX_CLK */
|
||||
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
|
||||
|
|
|
@ -47,16 +47,10 @@ static void mainboard_enable(device_t dev)
|
|||
|
||||
hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH);
|
||||
hudson_enable_smi_generation();
|
||||
/*
|
||||
* The mainboard is the first place that we get control in ramstage. Check
|
||||
* for S3 resume and call the appropriate AGESA/CIMx resume functions.
|
||||
*/
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
acpi_slp_type = acpi_get_sleep_type();
|
||||
if (acpi_slp_type == 3)
|
||||
|
||||
if (acpi_is_wakeup_s3())
|
||||
agesawrapper_fchs3earlyrestore();
|
||||
else
|
||||
#endif
|
||||
pavilion_cold_boot_init();
|
||||
|
||||
}
|
||||
|
|
|
@ -157,14 +157,6 @@ static void mainboard_enable(device_t dev)
|
|||
{
|
||||
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
|
||||
|
||||
/*
|
||||
* The mainboard is the first place that we get control in ramstage. Check
|
||||
* for S3 resume and call the appropriate AGESA/CIMx resume functions.
|
||||
*/
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
acpi_slp_type = acpi_get_sleep_type();
|
||||
#endif /* CONFIG_HAVE_ACPI_RESUME */
|
||||
|
||||
/* enable GPP CLK0 thru CLK3 (interleaved) */
|
||||
/* disable GPP CLK4 thru SLT_GFX_CLK */
|
||||
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
|
||||
|
|
|
@ -167,14 +167,6 @@ static void mainboard_enable(device_t dev)
|
|||
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
|
||||
dev->ops->init = init;
|
||||
|
||||
/*
|
||||
* The mainboard is the first place that we get control in ramstage. Check
|
||||
* for S3 resume and call the appropriate AGESA/CIMx resume functions.
|
||||
*/
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
acpi_slp_type = acpi_get_sleep_type();
|
||||
#endif
|
||||
|
||||
/* enable GPP CLK0 */
|
||||
/* disable GPP CLK1 thru SLT_GFX_CLK */
|
||||
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
|
||||
|
|
|
@ -134,14 +134,6 @@ static void mainboard_enable(device_t dev)
|
|||
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
|
||||
dev->ops->init = init;
|
||||
|
||||
/*
|
||||
* The mainboard is the first place that we get control in ramstage. Check
|
||||
* for S3 resume and call the appropriate AGESA/CIMx resume functions.
|
||||
*/
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
acpi_slp_type = acpi_get_sleep_type();
|
||||
#endif
|
||||
|
||||
/* enable GPP CLK0 thru CLK1 */
|
||||
/* disable GPP CLK2 thru SLT_GFX_CLK */
|
||||
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
|
||||
|
|
Loading…
Reference in New Issue