mb/google/poppy/variants/nami: Use GPP_B4 as Touchscreen Power Enable
Touchscreen power enable for Nami has moved from GBB_C22 to GPP_B4 in the latest schematics. BUG=b:74347464 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: I3b1794d44f25c0d42d082d63b9e3ec3dfcef7528 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25154 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -254,7 +254,7 @@ chip soc/intel/skylake
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register "probed" = "1"
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register "probed" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
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register "reset_delay_ms" = "20"
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register "reset_delay_ms" = "20"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)"
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register "enable_delay_ms" = "1"
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register "enable_delay_ms" = "1"
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register "has_power_resource" = "1"
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register "has_power_resource" = "1"
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device i2c 10 on end
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device i2c 10 on end
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@ -70,8 +70,8 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NC(GPP_B2),
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PAD_CFG_NC(GPP_B2),
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/* B3 : CPU_GP2 ==> TOUCHSCREEN_RST# */
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/* B3 : CPU_GP2 ==> TOUCHSCREEN_RST# */
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PAD_CFG_GPO(GPP_B3, 0, DEEP),
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PAD_CFG_GPO(GPP_B3, 0, DEEP),
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/* B4 : CPU_GP3 ==> NC */
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/* B4 : CPU_GP3 ==> EN_PP3300_DX_TOUCHSCREEN */
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PAD_CFG_NC(GPP_B4),
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PAD_CFG_GPO(GPP_B4, 0, DEEP),
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/* B5 : SRCCLKREQ0# ==> NC */
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/* B5 : SRCCLKREQ0# ==> NC */
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PAD_CFG_NC(GPP_B5),
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PAD_CFG_NC(GPP_B5),
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/* B6 : SRCCLKREQ1# ==> CLKREQ_PCIE#1 */
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/* B6 : SRCCLKREQ1# ==> CLKREQ_PCIE#1 */
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@ -155,8 +155,8 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
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/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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/* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */
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/* C22 : UART2_RTS# ==> NC */
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PAD_CFG_GPO(GPP_C22, 0, DEEP),
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PAD_CFG_NC(GPP_C22),
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/* C23 : UART2_CTS# ==> PCH_WP */
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/* C23 : UART2_CTS# ==> PCH_WP */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
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PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
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