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AMD RS780, SR5650: PcieTrainPort: Fix typo *i*gnoring in comment 

Reading the paste of code in a message to the mailing list [1],
a typo was spotted and found in one more place.

    $ git grep egnoring
    src/southbridge/amd/rs780/cmn.c:                         * egnoring the reversal case
    src/southbridge/amd/sr5650/sr5650.c:                     * egnoring the reversal case

These typos are there since when the code was committed and are
now corrected.

[1] http://www.coreboot.org/pipermail/coreboot/2013-April/075644.html

Change-Id: I55c65f71e4834f209b60d678f0d44bc2f4217099
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3062
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
This commit is contained in:
Paul Menzel 2013-04-10 11:33:37 +02:00 committed by Martin Roth
parent 573a1d6fa8
commit 6a1210901d
2 changed files with 2 additions and 2 deletions
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2
src/southbridge/amd/rs780/cmn.c
View File

@ -301,7 +301,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
/* 4 means 7:4 and 15:12
* 3 means 7:2 and 15:10
* 2 means 7:1 and 15:9
* egnoring the reversal case
* ignoring the reversal case
*/
lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF;
reg = nbpcie_ind_read_index(nb_dev, 0x65 | gfx_gpp_sb_sel);

2
src/southbridge/amd/sr5650/sr5650.c
View File

@ -202,7 +202,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
/* 4 means 7:4 and 15:12
* 3 means 7:2 and 15:10
* 2 means 7:1 and 15:9
* egnoring the reversal case
* ignoring the reversal case
*/
lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF;
reg = nbpcie_ind_read_index(nb_dev, 0x65 | gpp_sb_sel);