diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index 5c22ce1664..0aa76a5add 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -182,6 +182,8 @@ Device (PDRC)
 		Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT
 		Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM
 		Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
+		Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE)
+		Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE)
 	})
 
 	// Current Resource Settings
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 15a0b1b043..13c2dcd2bc 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -21,6 +21,9 @@ static void haswell_setup_bars(void)
 	pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
 	pci_write_config32(HOST_BRIDGE, DMIBAR + 4, 0);
 
+	mchbar_write32(EDRAMBAR, EDRAM_BASE_ADDRESS | 1);
+	mchbar_write32(GDXCBAR, GDXC_BASE_ADDRESS | 1);
+
 	/* Set C0000-FFFFF to access RAM on both reads and writes */
 	pci_write_config8(HOST_BRIDGE, PAM0, 0x30);
 	pci_write_config8(HOST_BRIDGE, PAM1, 0x33);
diff --git a/src/northbridge/intel/haswell/memmap.h b/src/northbridge/intel/haswell/memmap.h
index 92beeece49..fd2317fc68 100644
--- a/src/northbridge/intel/haswell/memmap.h
+++ b/src/northbridge/intel/haswell/memmap.h
@@ -9,8 +9,10 @@
 
 #define EP_BASE_SIZE		0x1000
 
+#define EDRAM_BASE_ADDRESS	0xfed80000
 #define EDRAM_BASE_SIZE		0x4000
 
+#define GDXC_BASE_ADDRESS	0xfed84000
 #define GDXC_BASE_SIZE		0x1000
 
 #define GFXVT_BASE_ADDRESS	0xfed90000ULL