GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

RD890: 64bit fixes 

Change-Id: I326c070398c72a877054969d3a03e6e427edc304
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11086
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Stefan Reinauer 2015-07-30 16:25:33 -07:00 committed by Stefan Reinauer
parent 59d0e040c8
commit 6a2df9a5e8
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/northbridge/amd/cimx/rd890/late.c
View File

@ -86,7 +86,8 @@ static void rd890_enable(device_t dev)
/* CIMX configuration defualt initialize */ /* CIMX configuration defualt initialize */
rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]);
if (gConfig.StandardHeader.CalloutPtr != NULL) { if (gConfig.StandardHeader.CalloutPtr != NULL) {
gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig,
(uintptr_t)dev, (VOID*)NbConfigPtr);
} }
/* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree
* After this call EP are fully operational on particular NB * After this call EP are fully operational on particular NB
@ -122,7 +123,7 @@ static void ioapic_init(struct device *dev)
void *ioapic_base; void *ioapic_base;
pci_write_config32(dev, 0xF8, 0x1); pci_write_config32(dev, 0xF8, 0x1);
ioapic_base = (void *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); ioapic_base = (void *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
clear_ioapic(ioapic_base); clear_ioapic(ioapic_base);
setup_ioapic(ioapic_base, 1); setup_ioapic(ioapic_base, 1);
} }