GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/stoneyridge: Use macros for PCI_DEVFN calls 

* Change all calls to PCI_DEVFN to macros
 * Remove CBB and CDB Kconfig since these are static for stoneyridge

BUG=b:62200746
TEST=build

Change-Id: I001c4ccd0ad7cf2047870b3618e13642144ddf56
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Chris Ching 2017-10-19 11:45:30 -06:00 committed by Chris Ching
parent c5ecd3e14d
commit 6a35fab272
6 changed files with 9 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/amd/stoneyridge/Kconfig
View File

@ -98,14 +98,6 @@ config CPU_ADDR_BITS
int
default 48
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config BOTTOMIO_POSITION
hex "Bottom of 32-bit IO space"
default 0xD0000000

3
src/soc/amd/stoneyridge/acpi.c
View File

@ -29,6 +29,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <soc/acpi.h>
#include <soc/pci_devs.h>
#include <soc/southbridge.h>
#include <soc/nvs.h>
@ -239,7 +240,7 @@ void generate_cpu_entries(device_t device)
device_t cdb_dev;
/* Stoney Ridge is single node, just report # of cores */
cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 5));
cdb_dev = dev_find_slot(0, NB_DEVFN);
cores = (pci_read_config32(cdb_dev, 0x84) & 0xff) + 1;
printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);

3
src/soc/amd/stoneyridge/dimmSpd.c
View File

@ -15,6 +15,7 @@
#include <device/pci_def.h>
#include <device/device.h>
#include <soc/pci_devs.h>
#include <stdlib.h>
/* warning: Porting.h includes an open #pragma pack(1) */
@ -27,7 +28,7 @@ AGESA_STATUS AmdMemoryReadSPD(UINT32 unused1, UINTN unused2,
AGESA_READ_SPD_PARAMS *info)
{
int spdAddress;
DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
DEVTREE_CONST struct device *dev = dev_find_slot(0, DCT_DEVFN);
DEVTREE_CONST struct soc_amd_stoneyridge_config *conf = dev->chip_info;
if ((dev == 0) || (conf == 0))

4
src/soc/amd/stoneyridge/include/soc/pci_devs.h
View File

@ -41,7 +41,7 @@
#define HDA0_DEV 0x1
#define HDA0_FUNC 1
#define HDA0_DEVID 015b3
#define HDA0_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC)
#define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC)
/* Host Bridge */
#define HOST_DEV 0x2
@ -155,7 +155,7 @@
#define HDA0_DEV 0x1
#define HDA0_FUNC 1
#define HDA0_DEVID 015b3
#define HDA0_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC)
#define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC)
/* Host Bridge */
#define HOST_DEV 0x2

2
src/soc/amd/stoneyridge/lpc.c
View File

@ -44,7 +44,7 @@ static void lpc_init(device_t dev)
* Enable the LPC Controller
* SMBus register 0x64 is not defined in public datasheet.
*/
sm_dev = dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC));
sm_dev = dev_find_slot(0, SMBUS_DEVFN);
dword = pci_read_config32(sm_dev, 0x64);
dword |= 1 << 20;
pci_write_config32(sm_dev, 0x64, dword);

4
src/soc/amd/stoneyridge/northbridge.c
View File

@ -338,12 +338,12 @@ void fam15_finalize(void *chip_info)
{
device_t dev;
u32 value;
dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
dev = dev_find_slot(0, GNB_DEVFN); /* clear IoapicSbFeatureEn */
pci_write_config32(dev, 0xf8, 0);
pci_write_config32(dev, 0xfc, 5); /* TODO: move it to dsdt.asl */
/* disable No Snoop */
dev = dev_find_slot(0, PCI_DEVFN(1, 1));
dev = dev_find_slot(0, HDA0_DEVFN);
value = pci_read_config32(dev, 0x60);
value &= ~(1 << 11);
pci_write_config32(dev, 0x60, value);