soc/amd/stoneyridge: Use macros for PCI_DEVFN calls
* Change all calls to PCI_DEVFN to macros * Remove CBB and CDB Kconfig since these are static for stoneyridge BUG=b:62200746 TEST=build Change-Id: I001c4ccd0ad7cf2047870b3618e13642144ddf56 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -98,14 +98,6 @@ config CPU_ADDR_BITS
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int
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int
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default 48
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default 48
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config CBB
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hex
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default 0x0
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config CDB
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hex
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default 0x18
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config BOTTOMIO_POSITION
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config BOTTOMIO_POSITION
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hex "Bottom of 32-bit IO space"
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hex "Bottom of 32-bit IO space"
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default 0xD0000000
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default 0xD0000000
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@ -29,6 +29,7 @@
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci.h>
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#include <soc/acpi.h>
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#include <soc/acpi.h>
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#include <soc/pci_devs.h>
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#include <soc/southbridge.h>
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#include <soc/southbridge.h>
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#include <soc/nvs.h>
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#include <soc/nvs.h>
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@ -239,7 +240,7 @@ void generate_cpu_entries(device_t device)
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device_t cdb_dev;
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device_t cdb_dev;
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/* Stoney Ridge is single node, just report # of cores */
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/* Stoney Ridge is single node, just report # of cores */
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cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 5));
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cdb_dev = dev_find_slot(0, NB_DEVFN);
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cores = (pci_read_config32(cdb_dev, 0x84) & 0xff) + 1;
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cores = (pci_read_config32(cdb_dev, 0x84) & 0xff) + 1;
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printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
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printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
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@ -15,6 +15,7 @@
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#include <device/pci_def.h>
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#include <device/pci_def.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <soc/pci_devs.h>
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#include <stdlib.h>
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#include <stdlib.h>
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/* warning: Porting.h includes an open #pragma pack(1) */
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/* warning: Porting.h includes an open #pragma pack(1) */
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@ -27,7 +28,7 @@ AGESA_STATUS AmdMemoryReadSPD(UINT32 unused1, UINTN unused2,
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AGESA_READ_SPD_PARAMS *info)
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AGESA_READ_SPD_PARAMS *info)
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{
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{
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int spdAddress;
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int spdAddress;
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DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
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DEVTREE_CONST struct device *dev = dev_find_slot(0, DCT_DEVFN);
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DEVTREE_CONST struct soc_amd_stoneyridge_config *conf = dev->chip_info;
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DEVTREE_CONST struct soc_amd_stoneyridge_config *conf = dev->chip_info;
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if ((dev == 0) || (conf == 0))
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if ((dev == 0) || (conf == 0))
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@ -41,7 +41,7 @@
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#define HDA0_DEV 0x1
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#define HDA0_DEV 0x1
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#define HDA0_FUNC 1
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#define HDA0_FUNC 1
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#define HDA0_DEVID 015b3
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#define HDA0_DEVID 015b3
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#define HDA0_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC)
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#define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC)
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/* Host Bridge */
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/* Host Bridge */
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#define HOST_DEV 0x2
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#define HOST_DEV 0x2
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@ -155,7 +155,7 @@
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#define HDA0_DEV 0x1
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#define HDA0_DEV 0x1
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#define HDA0_FUNC 1
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#define HDA0_FUNC 1
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#define HDA0_DEVID 015b3
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#define HDA0_DEVID 015b3
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#define HDA0_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC)
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#define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC)
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/* Host Bridge */
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/* Host Bridge */
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#define HOST_DEV 0x2
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#define HOST_DEV 0x2
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@ -44,7 +44,7 @@ static void lpc_init(device_t dev)
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* Enable the LPC Controller
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* Enable the LPC Controller
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* SMBus register 0x64 is not defined in public datasheet.
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* SMBus register 0x64 is not defined in public datasheet.
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*/
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*/
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sm_dev = dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC));
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sm_dev = dev_find_slot(0, SMBUS_DEVFN);
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dword = pci_read_config32(sm_dev, 0x64);
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dword = pci_read_config32(sm_dev, 0x64);
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dword |= 1 << 20;
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dword |= 1 << 20;
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pci_write_config32(sm_dev, 0x64, dword);
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pci_write_config32(sm_dev, 0x64, dword);
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@ -338,12 +338,12 @@ void fam15_finalize(void *chip_info)
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{
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{
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device_t dev;
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device_t dev;
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u32 value;
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u32 value;
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dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
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dev = dev_find_slot(0, GNB_DEVFN); /* clear IoapicSbFeatureEn */
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pci_write_config32(dev, 0xf8, 0);
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pci_write_config32(dev, 0xf8, 0);
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pci_write_config32(dev, 0xfc, 5); /* TODO: move it to dsdt.asl */
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pci_write_config32(dev, 0xfc, 5); /* TODO: move it to dsdt.asl */
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/* disable No Snoop */
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/* disable No Snoop */
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dev = dev_find_slot(0, PCI_DEVFN(1, 1));
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dev = dev_find_slot(0, HDA0_DEVFN);
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value = pci_read_config32(dev, 0x60);
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value = pci_read_config32(dev, 0x60);
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value &= ~(1 << 11);
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value &= ~(1 << 11);
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pci_write_config32(dev, 0x60, value);
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pci_write_config32(dev, 0x60, value);
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