From 6a3a3e5c982aa3f04f47126c3ed47b060e49c78e Mon Sep 17 00:00:00 2001
From: "Ronald G. Minnich" <rminnich@gmail.com>
Date: Mon, 30 Jun 2003 17:23:35 +0000
Subject: [PATCH] placeholder crap for sio

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
---
 src/superio/NSC/pc87360/superio.c | 45 +++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/src/superio/NSC/pc87360/superio.c b/src/superio/NSC/pc87360/superio.c
index e69de29bb2..451bf4b8c4 100644
--- a/src/superio/NSC/pc87360/superio.c
+++ b/src/superio/NSC/pc87360/superio.c
@@ -0,0 +1,45 @@
+/* $Id$ */
+/* Copyright 2000  AG Electronics Ltd. */
+/* This code is distributed without warranty under the GPL v2 (see COPYING) */
+
+#include <types.h>
+#include <arch/io.h>
+
+#ifndef PNP_INDEX_REG
+#define PNP_INDEX_REG	0x15C
+#endif
+#ifndef PNP_DATA_REG
+#define PNP_DATA_REG	0x15D
+#endif
+#ifndef SIO_COM1
+#define SIO_COM1_BASE	0x3F8
+#endif
+#ifndef SIO_COM2
+#define SIO_COM2_BASE	0x2F8
+#endif
+
+static
+void pnp_output(char address, char data)
+{
+    outb(address, PNP_INDEX_REG);
+    outb(data, PNP_DATA_REG);
+}
+
+static
+void sio_enable(void)
+{
+    /* Enable Super IO Chip */
+    pnp_output(0x07, 6); /* LD 6 = UART1 */
+    pnp_output(0x30, 0); /* Dectivate */
+    pnp_output(0x60, SIO_COM1_BASE >> 8); /* IO Base */
+    pnp_output(0x61, SIO_COM1_BASE & 0xFF); /* IO Base */
+    pnp_output(0x30, 1); /* Activate */
+}
+
+struct superio_control superio_NSC_pc87360_control = {
+	pre_pci_init:   (void *)0,
+	init:           (void *)0,
+	finishup:       (void *)0,
+	defaultport:    SIO_COM1_BASE,
+	name:           "NSC pc87360"
+};