zero warning days.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -20,7 +20,6 @@
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*/
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#include <spd.h>
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#include <sdram_mode.h>
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#include <delay.h>
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#include <stdlib.h>
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#include "i440bx.h"
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@ -20,7 +20,6 @@
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*/
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#include <spd.h>
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#include <sdram_mode.h>
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#include <delay.h>
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#include <stdlib.h>
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#include "i440lx.h"
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@ -21,7 +21,6 @@
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*/
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#include <spd.h>
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#include <sdram_mode.h>
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#include <delay.h>
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#include "i82810.h"
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@ -20,7 +20,6 @@
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*/
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#include <spd.h>
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#include <sdram_mode.h>
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#include <delay.h>
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#include "lib/debug.c"
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#include "i82830.h"
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@ -29,7 +29,6 @@
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/* ported from Via VT8263 Code*/
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#include <spd.h>
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#include <sdram_mode.h>
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#include <delay.h>
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#include <cpu/x86/mtrr.h>
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#include "cn400.h"
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@ -21,7 +21,6 @@
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*/
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#include <spd.h>
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#include <sdram_mode.h>
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#include <delay.h>
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#include "cn700.h"
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@ -20,7 +20,6 @@
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#include <types.h>
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#include <spd.h>
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#include <spd_ddr2.h>
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#include <sdram_mode.h>
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#include <delay.h>
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#include "cx700_registers.h"
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@ -18,7 +18,6 @@
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*/
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#include <spd.h>
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#include <sdram_mode.h>
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#include <delay.h>
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#if CONFIG_DEBUG_RAM_SETUP
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@ -34,6 +34,7 @@
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#define CLK_CNTL_INDEX 0x8
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#define CLK_CNTL_DATA 0xC
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#if 0
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static u32 clkind_read(device_t dev, u32 index)
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{
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u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
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*(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F;
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return *(u32*)(gfx_bar2+CLK_CNTL_DATA);
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}
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#endif
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static void clkind_write(device_t dev, u32 index, u32 data)
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{
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@ -73,8 +75,6 @@ static void rs690_gfx_read_resources(device_t dev)
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static void internal_gfx_pci_dev_init(struct device *dev)
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{
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u16 deviceid, vendorid;
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struct southbridge_amd_rs690_config *cfg =
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(struct southbridge_amd_rs690_config *)dev->chip_info;
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deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
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vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
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printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
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@ -18,39 +18,10 @@
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*/
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <reset.h>
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#define PCI_DEV(BUS, DEV, FN) ( \
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(((BUS) & 0xFFF) << 20) | \
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(((DEV) & 0x1F) << 15) | \
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(((FN) & 0x7) << 12))
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typedef u32 device_t;
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static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
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{
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unsigned addr;
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addr = (dev>>4) | where;
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outl(0x80000000 | (addr & ~3), 0xCF8);
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outb(value, 0xCFC + (addr & 3));
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}
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static void pci_write_config32(device_t dev, unsigned where, unsigned value)
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{
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unsigned addr;
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addr = (dev>>4) | where;
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outl(0x80000000 | (addr & ~3), 0xCF8);
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outl(value, 0xCFC);
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}
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static unsigned pci_read_config32(device_t dev, unsigned where)
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{
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unsigned addr;
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addr = (dev>>4) | where;
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outl(0x80000000 | (addr & ~3), 0xCF8);
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return inl(0xCFC);
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}
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#include "../../../northbridge/amd/amdk8/reset_test.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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void hard_reset(void)
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{
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@ -20,6 +20,7 @@
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#ifndef _SB700_EARLY_SETUP_C_
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#define _SB700_EARLY_SETUP_C_
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#include <reset.h>
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#include <arch/cpu.h>
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#include "sb700.h"
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#include "sb700_smbus.c"
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pmio_write(0x89, 0x10);
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}
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static void hard_reset(void)
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void hard_reset(void)
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{
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set_bios_reset();
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outb(0x0e, 0x0cf9);
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}
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static void soft_reset(void)
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void soft_reset(void)
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{
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set_bios_reset();
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/* link reset */
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