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mb/google/zork: Set S0IX_SLP_L high in S0, low in S3 

This is used as a signal to show the system state.  It hadn't been used
up to this point as we're not currently using S0i3, but the fingerprint
sensor will use it to go into a low power mode, so set it appropriately
on Trembyle.  Dalboz devices don't use the FPMCU, but set there as well
so that the state matches.

BUG=b:174695987
TEST=Verify GPIO state in S0 and S3 with the EC
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibc725905909830d44f77c2498a26edf6d7a3dc05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48255
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Vincent Palatin <vpalatin@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2020-12-02 16:37:58 -07:00 committed by Felix Held
parent 361a5c0952
commit 6a62cc85e6
2 changed files with 8 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
View File

@ -30,8 +30,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
/* TOUCHPAD_INT_ODL */ /* TOUCHPAD_INT_ODL */
PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW),
/* S0iX SLP - (unused - goes to EC */ /* S0iX SLP - goes to EC */
PAD_NC(GPIO_10), PAD_GPO(GPIO_10, HIGH),
/* EC_IN_RW_OD */ /* EC_IN_RW_OD */
PAD_GPI(GPIO_11, PULL_NONE), PAD_GPI(GPIO_11, PULL_NONE),
/* USI_INT_ODL */ /* USI_INT_ODL */
@ -302,6 +302,8 @@ const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int
} }
static const struct soc_amd_gpio gpio_sleep_table[] = { static const struct soc_amd_gpio gpio_sleep_table[] = {
/* S0iX SLP */
PAD_GPO(GPIO_10, LOW),
/* PCIE_RST1_L */ /* PCIE_RST1_L */
PAD_GPO(GPIO_27, LOW), PAD_GPO(GPIO_27, LOW),
/* /*

6
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
View File

@ -32,8 +32,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
/* TOUCHPAD_INT_ODL */ /* TOUCHPAD_INT_ODL */
PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW),
/* S0iX SLP - (unused - goes to EC & FPMCU */ /* S0iX SLP - goes to EC & FPMCU */
PAD_NC(GPIO_10), PAD_GPO(GPIO_10, HIGH),
/* USI_INT_ODL */ /* USI_INT_ODL */
PAD_GPI(GPIO_12, PULL_NONE), PAD_GPI(GPIO_12, PULL_NONE),
/* EN_PWR_TOUCHPAD_PS2 */ /* EN_PWR_TOUCHPAD_PS2 */
@ -342,6 +342,8 @@ const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int
} }
static const struct soc_amd_gpio gpio_sleep_table[] = { static const struct soc_amd_gpio gpio_sleep_table[] = {
/* S0iX SLP */
PAD_GPO(GPIO_10, LOW),
/* NVME_AUX_RESET_L */ /* NVME_AUX_RESET_L */
PAD_GPO(GPIO_40, LOW), PAD_GPO(GPIO_40, LOW),
/* EN_PWR_CAMERA */ /* EN_PWR_CAMERA */