soc/intel/alderlake: Disable SaGV reordering

Disable re-ordering SaGv point on warm reset so that most
performant SaGv point is picked after memory training and
boot time is reduced.

BUG=b:268546941
TEST=Observe boot time improvement with these two UPDs set

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I44a1c054d52bb8585a320bb8a52a8f137e639804
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74721
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/alderlake/chipset.cb

@@ -93,6 +93,9 @@ chip soc/intel/alderlake
 	# Reduce the size of BasicMemoryTests to speed up the boot time.
 	register "lower_basic_mem_test_size" = "true"
 
+	# Disable SaGV reordering operation to start with SaGV point 4 and reduce boot time.
+	register "disable_sagv_reorder" = "true"
+
 	# NOTE: if any variant wants to override this value, use the same format
 	# as register "common_soc_config.pch_thermal_trip" = "value", instead of
 	# putting it under register "common_soc_config" in overridetree.cb file.