From 6a6d524b0a6383dd054a2e810c24789b5a033b16 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 23 Mar 2023 19:25:20 +0100 Subject: [PATCH] soc/amd/mendocino: add and use missing cpu_vid_8 pstate_msr field Mendocino uses the SVI3 standard for CPU core voltage control which uses 9 data bits instead of the 8 in the SVI2 case and also calculates the actual voltages with a different formula. The Mendocino code uses the correct formula since commit 8d2bfbce23f6 ("soc/amd/sabrina/acpi: Correct VID decoding on Sabrina"), but the MSR definition in the PPR hasn't been updated to show the additional bit. The definition of the register that is mirrored by these MSRs descries this 9th CPU voltage ID bit though. Since this bit is expected to be zero, this shouldn't cause a change in behavior. Signed-off-by: Felix Held Change-Id: I05acd239300836a34e40cd3f31ea819b79766e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73969 Reviewed-by: Fred Reitberger Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/soc/amd/mendocino/acpi.c | 2 +- src/soc/amd/mendocino/include/soc/msr.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 3248adb6b5..5bc893c458 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -139,7 +139,7 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg) uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw; /* Core voltage ID */ - core_vid = pstate_reg.cpu_vid_0_7; + core_vid = pstate_reg.cpu_vid_0_7 | pstate_reg.cpu_vid_8 << 8; /* Current value in amps */ current_value_amps = pstate_reg.idd_value; diff --git a/src/soc/amd/mendocino/include/soc/msr.h b/src/soc/amd/mendocino/include/soc/msr.h index 39babf46d0..f8e6092afe 100644 --- a/src/soc/amd/mendocino/include/soc/msr.h +++ b/src/soc/amd/mendocino/include/soc/msr.h @@ -11,7 +11,8 @@ union pstate_msr { uint64_t cpu_vid_0_7 : 8; /* [14..21] */ uint64_t idd_value : 8; /* [22..29] */ uint64_t idd_div : 2; /* [30..31] */ - uint64_t : 31; /* [32..62] */ + uint64_t cpu_vid_8 : 1; /* [32..32] */ + uint64_t : 30; /* [33..62] */ uint64_t pstate_en : 1; /* [63..63] */ }; uint64_t raw;