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bd82x6x/ibexpeak: Make DRAM reset gate GPIO configurable 

DRAM reset gate GPIO is different on different mobos move it to hidden config
with 60 (current value) as default.

Set it to 10 for Lenovo X201.

Change-Id: I4f3b6876d7c33d4966315091b63a76a9a0064c16
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4622
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Vladimir Serbinenko 2014-01-05 11:37:32 +01:00
parent ffd4a610ba
commit 6a7aeb3b35
5 changed files with 82 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/lenovo/x201/Kconfig
View File

@ -43,6 +43,10 @@ config IRQ_SLOT_COUNT
int int
default 18 default 18
config DRAM_RESET_GATE_GPIO
int
default 10
config MAX_CPUS config MAX_CPUS
int int
default 4 default 4

4
src/southbridge/intel/bd82x6x/Kconfig
View File

@ -45,6 +45,10 @@ config EHCI_DEBUG_OFFSET
hex hex
default 0xa0 default 0xa0
config DRAM_RESET_GATE_GPIO
int
default 60
config BOOTBLOCK_SOUTHBRIDGE_INIT config BOOTBLOCK_SOUTHBRIDGE_INIT
string string
default "southbridge/intel/bd82x6x/bootblock.c" default "southbridge/intel/bd82x6x/bootblock.c"

54
src/southbridge/intel/bd82x6x/smihandler.c
View File

@ -290,6 +290,31 @@ static void busmaster_disable_on_bus(int bus)
} }
} }
static void southbridge_gate_memory_reset_real(int offset,
u16 use, u16 io, u16 lvl)
{
u32 reg32;
/* Make sure it is set as GPIO */
reg32 = inl(use);
if (!(reg32 & (1 << offset))) {
reg32 |= (1 << offset);
outl(reg32, use);
}
/* Make sure it is set as output */
reg32 = inl(io);
if (reg32 & (1 << offset)) {
reg32 &= ~(1 << offset);
outl(reg32, io);
}
/* Drive the output low */
reg32 = inl(lvl);
reg32 &= ~(1 << offset);
outl(reg32, lvl);
}
/* /*
* Drive GPIO 60 low to gate memory reset in S3. * Drive GPIO 60 low to gate memory reset in S3.
* *
@ -298,31 +323,22 @@ static void busmaster_disable_on_bus(int bus)
*/ */
static void southbridge_gate_memory_reset(void) static void southbridge_gate_memory_reset(void)
{ {
u32 reg32;
u16 gpiobase; u16 gpiobase;
gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
if (!gpiobase) if (!gpiobase)
return; return;
/* Make sure it is set as GPIO */ if (CONFIG_DRAM_RESET_GATE_GPIO >= 32)
reg32 = inl(gpiobase + GPIO_USE_SEL2); southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO - 32,
if (!(reg32 & (1 << 28))) { gpiobase + GPIO_USE_SEL2,
reg32 |= (1 << 28); gpiobase + GP_IO_SEL2,
outl(reg32, gpiobase + GPIO_USE_SEL2); gpiobase + GP_LVL2);
} else
southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO,
/* Make sure it is set as output */ gpiobase + GPIO_USE_SEL,
reg32 = inl(gpiobase + GP_IO_SEL2); gpiobase + GP_IO_SEL,
if (reg32 & (1 << 28)) { gpiobase + GP_LVL);
reg32 &= ~(1 << 28);
outl(reg32, gpiobase + GP_IO_SEL2);
}
/* Drive the output low */
reg32 = inl(gpiobase + GP_LVL2);
reg32 &= ~(1 << 28);
outl(reg32, gpiobase + GP_LVL2);
} }
static void xhci_sleep(u8 slp_typ) static void xhci_sleep(u8 slp_typ)

4
src/southbridge/intel/ibexpeak/Kconfig
View File

@ -43,6 +43,10 @@ config EHCI_DEBUG_OFFSET
hex hex
default 0xa0 default 0xa0
config DRAM_RESET_GATE_GPIO
int
default 60
config BOOTBLOCK_SOUTHBRIDGE_INIT config BOOTBLOCK_SOUTHBRIDGE_INIT
string string
default "southbridge/intel/bd82x6x/bootblock.c" default "southbridge/intel/bd82x6x/bootblock.c"

54
src/southbridge/intel/ibexpeak/smihandler.c
View File

@ -290,6 +290,31 @@ static void busmaster_disable_on_bus(int bus)
} }
} }
static void southbridge_gate_memory_reset_real(int offset,
u16 use, u16 io, u16 lvl)
{
u32 reg32;
/* Make sure it is set as GPIO */
reg32 = inl(use);
if (!(reg32 & (1 << offset))) {
reg32 |= (1 << offset);
outl(reg32, use);
}
/* Make sure it is set as output */
reg32 = inl(io);
if (reg32 & (1 << offset)) {
reg32 &= ~(1 << offset);
outl(reg32, io);
}
/* Drive the output low */
reg32 = inl(lvl);
reg32 &= ~(1 << offset);
outl(reg32, lvl);
}
/* /*
* Drive GPIO 60 low to gate memory reset in S3. * Drive GPIO 60 low to gate memory reset in S3.
* *
@ -298,31 +323,22 @@ static void busmaster_disable_on_bus(int bus)
*/ */
static void southbridge_gate_memory_reset(void) static void southbridge_gate_memory_reset(void)
{ {
u32 reg32;
u16 gpiobase; u16 gpiobase;
gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
if (!gpiobase) if (!gpiobase)
return; return;
/* Make sure it is set as GPIO */ if (CONFIG_DRAM_RESET_GATE_GPIO >= 32)
reg32 = inl(gpiobase + GPIO_USE_SEL2); southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO - 32,
if (!(reg32 & (1 << 28))) { gpiobase + GPIO_USE_SEL2,
reg32 |= (1 << 28); gpiobase + GP_IO_SEL2,
outl(reg32, gpiobase + GPIO_USE_SEL2); gpiobase + GP_LVL2);
} else
southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO,
/* Make sure it is set as output */ gpiobase + GPIO_USE_SEL,
reg32 = inl(gpiobase + GP_IO_SEL2); gpiobase + GP_IO_SEL,
if (reg32 & (1 << 28)) { gpiobase + GP_LVL);
reg32 &= ~(1 << 28);
outl(reg32, gpiobase + GP_IO_SEL2);
}
/* Drive the output low */
reg32 = inl(gpiobase + GP_LVL2);
reg32 &= ~(1 << 28);
outl(reg32, gpiobase + GP_LVL2);
} }
static void xhci_sleep(u8 slp_typ) static void xhci_sleep(u8 slp_typ)