cpu/intel/car: Prepare for some POSTCAR_STAGE support
The file cache_as_ram_ht.inc is used across a variety of CPUs and northbridges. We need to split it anyway for future C_ENVIRONMENT_BOOTBLOCK and verstage work. Split and rename the files, remove code that is globally implemented in POSTCAR_STAGE framework already. Change-Id: I2ba67772328fce3d5d1ae34c36aea8dcdcc56b87 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
parent
8168046432
commit
6a8ce0d250
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@ -0,0 +1,376 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
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* Copyright (C) 2007-2008 coresystems GmbH
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* Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/post_code.h>
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#include <cpu/x86/lapic_def.h>
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/* Macro to access Local APIC registers at default base. */
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#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
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#define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff)
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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.code32
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_cache_as_ram_setup:
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/* Save the BIST result. */
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movl %eax, %ebp
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cache_as_ram:
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post_code(0x20)
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movl $LAPIC_BASE_MSR, %ecx
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rdmsr
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andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax
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jz ap_init
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/* Clear/disable fixed MTRRs */
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mov $fixed_mtrr_list_size, %ebx
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xor %eax, %eax
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xor %edx, %edx
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clear_fixed_mtrr:
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add $-2, %ebx
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movzwl fixed_mtrr_list(%ebx), %ecx
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wrmsr
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jnz clear_fixed_mtrr
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/* Figure put how many MTRRs we have, and clear them out */
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mov $MTRR_CAP_MSR, %ecx
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rdmsr
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movzb %al, %ebx /* Number of variable MTRRs */
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mov $MTRR_PHYS_BASE(0), %ecx
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xor %eax, %eax
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xor %edx, %edx
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clear_var_mtrr:
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wrmsr
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inc %ecx
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wrmsr
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inc %ecx
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dec %ebx
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jnz clear_var_mtrr
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post_code(0x21)
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/* Configure the default memory type to uncacheable. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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andl $(~0x00000cff), %eax
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wrmsr
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post_code(0x22)
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/* Determine CPU_ADDR_BITS and load PHYSMASK high
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* word to %edx.
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*/
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movl $0x80000000, %eax
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cpuid
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cmpl $0x80000008, %eax
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jc addrsize_no_MSR
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movl $0x80000008, %eax
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cpuid
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movb %al, %cl
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sub $32, %cl
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movl $1, %edx
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shl %cl, %edx
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subl $1, %edx
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jmp addrsize_set_high
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addrsize_no_MSR:
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movl $1, %eax
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cpuid
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andl $(1 << 6 | 1 << 17), %edx /* PAE or PSE36 */
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jz addrsize_set_high
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movl $0x0f, %edx
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/* Preload high word of address mask (in %edx) for Variable
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* MTRRs 0 and 1 and enable local APIC at default base.
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*/
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addrsize_set_high:
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xorl %eax, %eax
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movl $MTRR_PHYS_MASK(0), %ecx
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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wrmsr
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movl $LAPIC_BASE_MSR, %ecx
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not %edx
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movl %edx, %ebx
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rdmsr
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andl %ebx, %edx
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andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax
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orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax
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wrmsr
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bsp_init:
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post_code(0x23)
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/* Send INIT IPI to all excluding ourself. */
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movl LAPIC(ICR), %edi
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movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax
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1: movl %eax, (%edi)
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movl $0x30, %ecx
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2: pause
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dec %ecx
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jnz 2b
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movl (%edi), %ecx
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andl $LAPIC_ICR_BUSY, %ecx
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jnz 1b
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post_code(0x24)
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movl $1, %eax
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cpuid
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btl $28, %edx
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jnc sipi_complete
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bswapl %ebx
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movzx %bh, %edi
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cmpb $1, %bh
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jbe sipi_complete /* only one LAPIC ID in package */
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movl $0, %eax
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cpuid
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movb $1, %bl
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cmpl $4, %eax
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jb cores_counted
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movl $4, %eax
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movl $0, %ecx
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cpuid
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shr $26, %eax
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movb %al, %bl
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inc %bl
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cores_counted:
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movl %edi, %eax
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divb %bl
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cmpb $1, %al
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jbe sipi_complete /* only LAPIC ID of a core */
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/* For a hyper-threading processor, cache must not be disabled
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* on an AP on the same physical package with the BSP.
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*/
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hyper_threading_cpu:
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/* delay 10 ms */
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movl $10000, %ecx
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1: inb $0x80, %al
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dec %ecx
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jnz 1b
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post_code(0x25)
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/* Send Start IPI to all excluding ourself. */
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movl LAPIC(ICR), %edi
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movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax
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1: movl %eax, (%edi)
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movl $0x30, %ecx
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2: pause
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dec %ecx
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jnz 2b
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movl (%edi), %ecx
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andl $LAPIC_ICR_BUSY, %ecx
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jnz 1b
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/* delay 250 us */
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movl $250, %ecx
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1: inb $0x80, %al
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dec %ecx
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jnz 1b
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post_code(0x26)
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/* Wait for sibling CPU to start. */
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1: movl $(MTRR_PHYS_BASE(0)), %ecx
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rdmsr
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andl %eax, %eax
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jnz sipi_complete
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movl $0x30, %ecx
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2: pause
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dec %ecx
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jnz 2b
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jmp 1b
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ap_init:
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post_code(0x27)
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/* Do not disable cache (so BSP can enable it). */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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movl %eax, %cr0
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post_code(0x28)
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/* MTRR registers are shared between HT siblings. */
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movl $(MTRR_PHYS_BASE(0)), %ecx
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movl $(1 << 12), %eax
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xorl %edx, %edx
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wrmsr
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post_code(0x29)
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ap_halt:
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cli
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1: hlt
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jmp 1b
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sipi_complete:
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post_code(0x2a)
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/* Set Cache-as-RAM base address. */
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movl $(MTRR_PHYS_BASE(0)), %ecx
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movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
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xorl %edx, %edx
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wrmsr
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/* Set Cache-as-RAM mask. */
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movl $(MTRR_PHYS_MASK(0)), %ecx
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rdmsr
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movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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wrmsr
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post_code(0x2b)
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/* Enable MTRR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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orl $MTRR_DEF_TYPE_EN, %eax
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wrmsr
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/* Enable L2 cache Write-Back (WBINVD and FLUSH#).
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*
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* MSR is set when DisplayFamily_DisplayModel is one of:
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* 06_0x, 06_17, 06_1C
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*
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* Description says this bit enables use of WBINVD and FLUSH#.
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* Should this be set only after the system bus and/or memory
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* controller can successfully handle write cycles?
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*/
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#define EAX_FAMILY(a) (a << 8) /* for family <= 0fH */
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#define EAX_MODEL(a) (((a & 0xf0) << 12) | ((a & 0xf) << 4))
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movl $1, %eax
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cpuid
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movl %eax, %ebx
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andl $EAX_FAMILY(0x0f), %eax
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cmpl $EAX_FAMILY(0x06), %eax
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jne no_msr_11e
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movl %ebx, %eax
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andl $EAX_MODEL(0xff), %eax
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cmpl $EAX_MODEL(0x17), %eax
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je has_msr_11e
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cmpl $EAX_MODEL(0x1c), %eax
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je has_msr_11e
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andl $EAX_MODEL(0xf0), %eax
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cmpl $EAX_MODEL(0x00), %eax
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jne no_msr_11e
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has_msr_11e:
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movl $0x11e, %ecx
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rdmsr
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orl $(1 << 8), %eax
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wrmsr
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no_msr_11e:
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post_code(0x2c)
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/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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invd
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movl %eax, %cr0
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/* Clear the cache memory region. This will also fill up the cache. */
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cld
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xorl %eax, %eax
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movl $CACHE_AS_RAM_BASE, %edi
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movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
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rep stosl
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post_code(0x2d)
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/* Enable Cache-as-RAM mode by disabling cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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/* Enable cache for our code in Flash because we do XIP here */
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movl $MTRR_PHYS_BASE(1), %ecx
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xorl %edx, %edx
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/*
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* IMPORTANT: The following calculation _must_ be done at runtime. See
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* https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
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*/
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movl $copy_and_run, %eax
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andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
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orl $MTRR_TYPE_WRPROT, %eax
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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rdmsr
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movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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wrmsr
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post_code(0x2e)
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/* Enable cache. */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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movl %eax, %cr0
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/* Setup the stack. */
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movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
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movl %eax, %esp
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/* Restore the BIST result. */
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movl %ebp, %eax
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movl %esp, %ebp
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pushl %eax
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before_romstage:
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post_code(0x2f)
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/* Call romstage.c main function. */
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call romstage_main
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/* Should never see this postcode */
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post_code(POST_DEAD_CODE)
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.Lhlt:
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hlt
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jmp .Lhlt
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fixed_mtrr_list:
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.word MTRR_FIX_64K_00000
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.word MTRR_FIX_16K_80000
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.word MTRR_FIX_16K_A0000
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.word MTRR_FIX_4K_C0000
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.word MTRR_FIX_4K_C8000
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.word MTRR_FIX_4K_D0000
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.word MTRR_FIX_4K_D8000
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.word MTRR_FIX_4K_E0000
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.word MTRR_FIX_4K_E8000
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.word MTRR_FIX_4K_F0000
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.word MTRR_FIX_4K_F8000
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fixed_mtrr_list_size = . - fixed_mtrr_list
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_cache_as_ram_setup_end:
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@ -0,0 +1,45 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2007-2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/post_code.h>
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.code32
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.global chipset_teardown_car
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chipset_teardown_car:
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pop %esp
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post_code(0x30)
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/* Disable cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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post_code(0x31)
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/* Disable MTRR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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andl $(~MTRR_DEF_TYPE_EN), %eax
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wrmsr
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post_code(0x32)
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/* Return to caller. */
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jmp *%esp
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@ -23,7 +23,6 @@
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asmlinkage void *romstage_main(unsigned long bist)
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{
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int i;
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void *romstage_stack_after_car;
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const int num_guards = 4;
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const u32 stack_guard = 0xdeadbeef;
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u32 *stack_base;
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@ -52,10 +51,13 @@ asmlinkage void *romstage_main(unsigned long bist)
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printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
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}
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/* Get the stack to use after cache-as-ram is torn down. */
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romstage_stack_after_car = setup_stack_and_mtrrs();
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if (!IS_ENABLED(CONFIG_POSTCAR_STAGE))
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return setup_stack_and_mtrrs();
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return romstage_stack_after_car;
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platform_enter_postcar();
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/* We do not return. */
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return NULL;
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}
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asmlinkage void romstage_after_car(void)
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@ -8,5 +8,10 @@ subdirs-y += ../microcode
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subdirs-y += ../hyperthreading
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subdirs-y += ../speedstep
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ifneq ($(CONFIG_POSTCAR_STAGE),y)
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
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else
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cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
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postcar-y += ../car/p4-netburst/exit_car.S
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endif
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romstage-y += ../car/romstage.c
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|
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@ -8,5 +8,10 @@ subdirs-y += ../microcode
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subdirs-y += ../hyperthreading
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subdirs-y += ../speedstep
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ifneq ($(CONFIG_POSTCAR_STAGE),y)
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
|
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else
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||||
cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
|
||||
postcar-y += ../car/p4-netburst/exit_car.S
|
||||
endif
|
||||
romstage-y += ../car/romstage.c
|
||||
|
|
|
|||
|
|
@ -13,6 +13,10 @@ subdirs-y += ../microcode
|
|||
subdirs-y += ../hyperthreading
|
||||
subdirs-y += ../speedstep
|
||||
|
||||
ifneq ($(CONFIG_POSTCAR_STAGE),y)
|
||||
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
|
||||
romstage-y += ../car/romstage.c
|
||||
else
|
||||
cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
|
||||
postcar-y += ../car/p4-netburst/exit_car.S
|
||||
endif
|
||||
romstage-y += ../car/romstage.c
|
||||
|
|
|
|||
|
|
@ -9,5 +9,10 @@ subdirs-y += ../../x86/smm
|
|||
subdirs-y += ../microcode
|
||||
subdirs-y += ../hyperthreading
|
||||
|
||||
ifneq ($(CONFIG_POSTCAR_STAGE),y)
|
||||
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
|
||||
else
|
||||
cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
|
||||
postcar-y += ../car/p4-netburst/exit_car.S
|
||||
endif
|
||||
romstage-y += ../car/romstage.c
|
||||
|
|
|
|||
|
|
@ -22,6 +22,8 @@ void mainboard_romstage_entry(unsigned long bist);
|
|||
*/
|
||||
void *setup_stack_and_mtrrs(void);
|
||||
|
||||
void platform_enter_postcar(void);
|
||||
|
||||
/* romstage_main is called from the cache-as-ram assembly file to prepare
|
||||
* CAR stack guards.*/
|
||||
asmlinkage void *romstage_main(unsigned long bist);
|
||||
|
|
|
|||
Loading…
Reference in New Issue