nb/intel/sandybridge: Extract some IOSAV sequences into macros
This allows deduplicating them while preserving reproducibility. Tested with BUILD_TIMELESS=1, Asus P8H61-M PRO remains identical. Change-Id: Ic7d1a5732296bb678b9954f80508e9f7de7ff319 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Angel Pons
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@ -98,6 +98,618 @@ struct iosav_ssq {
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} addr_update;
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};
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#define ZQCS_SEQUENCE(slotrank, gap, post, wrap) \
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{ \
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/* DRAM command ZQCS */ \
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[0] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_ZQCS, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 1, \
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.cmd_delay_gap = gap, \
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.post_ssq_wait = post, \
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.data_direction = SSQ_NA, \
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}, \
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.sp_cmd_addr = { \
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.address = 0, \
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.rowbits = 6, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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.addr_update = { \
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.addr_wrap = wrap, \
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}, \
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}, \
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}
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#define PREA_SEQUENCE(t_rp, wrap) \
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{ \
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/* DRAM command PREA */ \
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[0] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_PRE, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 1, \
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.cmd_delay_gap = 3, \
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.post_ssq_wait = t_rp, \
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.data_direction = SSQ_NA, \
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}, \
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.sp_cmd_addr = { \
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.address = 1024, \
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.rowbits = 6, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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.addr_update = { \
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.addr_wrap = wrap, \
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}, \
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}, \
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}
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#define READ_MPR_SEQUENCE(t_mod, loops, gap, loops2, post2) \
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{ \
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/* \
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* DRAM command MRS \
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* \
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* Write MR3 MPR enable. In this mode only RD and RDA \
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* are allowed, and all reads return a predefined pattern. \
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*/ \
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[0] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_MRS, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 1, \
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.cmd_delay_gap = 3, \
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.post_ssq_wait = t_mod, \
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.data_direction = SSQ_NA, \
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}, \
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.sp_cmd_addr = { \
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.address = 4, \
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.rowbits = 6, \
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.bank = 3, \
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.rank = slotrank, \
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}, \
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}, \
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/* DRAM command RD */ \
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[1] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_RD, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = loops, \
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.cmd_delay_gap = gap, \
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.post_ssq_wait = 4, \
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.data_direction = SSQ_RD, \
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}, \
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.sp_cmd_addr = { \
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.address = 0, \
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.rowbits = 0, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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}, \
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/* DRAM command RD */ \
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[2] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_RD, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = loops2, \
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.cmd_delay_gap = 4, \
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.post_ssq_wait = post2, \
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.data_direction = SSQ_NA, \
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}, \
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.sp_cmd_addr = { \
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.address = 0, \
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.rowbits = 6, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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}, \
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/* \
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* DRAM command MRS \
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* \
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* Write MR3 MPR disable. \
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*/ \
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[3] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_MRS, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 1, \
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.cmd_delay_gap = 3, \
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.post_ssq_wait = t_mod, \
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.data_direction = SSQ_NA, \
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}, \
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.sp_cmd_addr = { \
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.address = 0, \
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.rowbits = 6, \
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.bank = 3, \
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.rank = slotrank, \
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}, \
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}, \
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}
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#define MISC_WRITE_SEQUENCE(gap0, loops0, gap1, loops2, wrap2) \
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{ \
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/* DRAM command ACT */ \
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[0] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_ACT, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = loops0, \
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.cmd_delay_gap = gap0, \
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.post_ssq_wait = ctrl->tRCD, \
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.data_direction = SSQ_NA, \
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}, \
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.sp_cmd_addr = { \
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.address = 0, \
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.rowbits = 6, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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.addr_update = { \
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.inc_bank = loops0 == 1 ? 0 : 1, \
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.addr_wrap = loops0 == 1 ? 0 : 18, \
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}, \
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}, \
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/* DRAM command NOP */ \
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[1] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_NOP, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 1, \
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.cmd_delay_gap = gap1, \
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.post_ssq_wait = 4, \
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.data_direction = SSQ_WR, \
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}, \
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.sp_cmd_addr = { \
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.address = 8, \
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.rowbits = 0, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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.addr_update = { \
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.addr_wrap = 31, \
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}, \
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}, \
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/* DRAM command WR */ \
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[2] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_WR, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = loops2, \
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.cmd_delay_gap = 4, \
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.post_ssq_wait = 4, \
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.data_direction = SSQ_WR, \
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}, \
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.sp_cmd_addr = { \
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.address = 0, \
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.rowbits = 0, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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.addr_update = { \
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.inc_addr_8 = 1, \
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.addr_wrap = wrap2, \
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}, \
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}, \
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/* DRAM command NOP */ \
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[3] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_NOP, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 1, \
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.cmd_delay_gap = 3, \
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.post_ssq_wait = ctrl->CWL + ctrl->tWTR + 5, \
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.data_direction = SSQ_WR, \
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}, \
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.sp_cmd_addr = { \
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.address = 8, \
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.rowbits = 0, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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.addr_update = { \
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.addr_wrap = 31, \
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}, \
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}, \
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}
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#define COMMAND_TRAINING_SEQUENCE(ctr) \
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{ \
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/* DRAM command ACT */ \
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[0] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_ACT, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 8, \
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.cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), \
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.post_ssq_wait = ctrl->tRCD, \
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.data_direction = SSQ_NA, \
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}, \
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.sp_cmd_addr = { \
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.address = ctr, \
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.rowbits = 6, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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.addr_update = { \
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.inc_bank = 1, \
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.addr_wrap = 18, \
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}, \
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}, \
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/* DRAM command WR */ \
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[1] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_WR, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 32, \
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.cmd_delay_gap = 4, \
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.post_ssq_wait = ctrl->CWL + ctrl->tWTR + 8, \
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.data_direction = SSQ_WR, \
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}, \
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.sp_cmd_addr = { \
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.address = 0, \
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.rowbits = 0, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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.addr_update = { \
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.inc_addr_8 = 1, \
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.addr_wrap = 18, \
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.lfsr_upd = 3, \
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.lfsr_xors = 2, \
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}, \
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}, \
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/* DRAM command RD */ \
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[2] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_RD, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 32, \
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.cmd_delay_gap = 4, \
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.post_ssq_wait = MAX(ctrl->tRTP, 8), \
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.data_direction = SSQ_RD, \
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}, \
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.sp_cmd_addr = { \
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.address = 0, \
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.rowbits = 0, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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.addr_update = { \
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.inc_addr_8 = 1, \
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.addr_wrap = 18, \
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.lfsr_upd = 3, \
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.lfsr_xors = 2, \
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}, \
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}, \
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/* DRAM command PRE */ \
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[3] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_PRE, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 1, \
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.cmd_delay_gap = 4, \
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.post_ssq_wait = 15, \
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.data_direction = SSQ_NA, \
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}, \
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.sp_cmd_addr = { \
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.address = 1024, \
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.rowbits = 6, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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.addr_update = { \
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.addr_wrap = 18, \
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}, \
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}, \
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}
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#define WRITE_DATA_SEQUENCE \
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{ \
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/* DRAM command ACT */ \
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[0] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_ACT, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 4, \
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.cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), \
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.post_ssq_wait = ctrl->tRCD, \
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.data_direction = SSQ_NA, \
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}, \
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.sp_cmd_addr = { \
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.address = 0, \
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.rowbits = 6, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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.addr_update = { \
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.inc_bank = 0, \
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.addr_wrap = 18, \
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}, \
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}, \
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/* DRAM command WR */ \
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[1] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_WR, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 32, \
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.cmd_delay_gap = 20, \
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.post_ssq_wait = ctrl->CWL + ctrl->tWTR + 8, \
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.data_direction = SSQ_WR, \
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}, \
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.sp_cmd_addr = { \
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.address = 0, \
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.rowbits = 0, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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.addr_update = { \
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.inc_addr_8 = 1, \
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.addr_wrap = 18, \
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}, \
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}, \
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/* DRAM command RD */ \
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[2] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_RD, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 32, \
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.cmd_delay_gap = 20, \
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.post_ssq_wait = MAX(ctrl->tRTP, 8), \
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.data_direction = SSQ_RD, \
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}, \
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.sp_cmd_addr = { \
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.address = 0, \
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.rowbits = 0, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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.addr_update = { \
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.inc_addr_8 = 1, \
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.addr_wrap = 18, \
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}, \
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}, \
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/* DRAM command PRE */ \
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[3] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_PRE, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 1, \
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.cmd_delay_gap = 3, \
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.post_ssq_wait = ctrl->tRP, \
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.data_direction = SSQ_NA, \
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}, \
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.sp_cmd_addr = { \
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.address = 1024, \
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.rowbits = 6, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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}, \
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}
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#define AGGRESSIVE_WRITE_READ_SEQUENCE \
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{ \
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/* DRAM command ACT */ \
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[0] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_ACT, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 4, \
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.cmd_delay_gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), \
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.post_ssq_wait = ctrl->tRCD, \
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.data_direction = SSQ_NA, \
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}, \
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.sp_cmd_addr = { \
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.address = 0, \
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.rowbits = 6, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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.addr_update = { \
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.inc_bank = 1, \
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.addr_wrap = 18, \
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}, \
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}, \
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/* DRAM command WR */ \
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[1] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_WR, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 480, \
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.cmd_delay_gap = 4, \
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.post_ssq_wait = ctrl->tWTR + ctrl->CWL + 8, \
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.data_direction = SSQ_WR, \
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}, \
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.sp_cmd_addr = { \
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.address = 0, \
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.rowbits = 0, \
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.bank = 0, \
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.rank = slotrank, \
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}, \
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.addr_update = { \
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.inc_addr_8 = 1, \
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.addr_wrap = 18, \
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}, \
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}, \
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/* DRAM command RD */ \
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[2] = { \
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.sp_cmd_ctrl = { \
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.command = IOSAV_RD, \
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.ranksel_ap = 1, \
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}, \
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.subseq_ctrl = { \
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.cmd_executions = 480, \
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.cmd_delay_gap = 4, \
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.post_ssq_wait = MAX(ctrl->tRTP, 8), \
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.data_direction = SSQ_RD, \
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}, \
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.sp_cmd_addr = { \
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.address = 0, \
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.rowbits = 0, \
|
||||
.bank = 0, \
|
||||
.rank = slotrank, \
|
||||
}, \
|
||||
.addr_update = { \
|
||||
.inc_addr_8 = 1, \
|
||||
.addr_wrap = 18, \
|
||||
}, \
|
||||
}, \
|
||||
/* DRAM command PRE */ \
|
||||
[3] = { \
|
||||
.sp_cmd_ctrl = { \
|
||||
.command = IOSAV_PRE, \
|
||||
.ranksel_ap = 1, \
|
||||
}, \
|
||||
.subseq_ctrl = { \
|
||||
.cmd_executions = 1, \
|
||||
.cmd_delay_gap = 4, \
|
||||
.post_ssq_wait = ctrl->tRP, \
|
||||
.data_direction = SSQ_NA, \
|
||||
}, \
|
||||
.sp_cmd_addr = { \
|
||||
.address = 1024, \
|
||||
.rowbits = 6, \
|
||||
.bank = 0, \
|
||||
.rank = slotrank, \
|
||||
}, \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define MEMORY_TEST_SEQUENCE \
|
||||
{ \
|
||||
/* DRAM command ACT */ \
|
||||
[0] = { \
|
||||
.sp_cmd_ctrl = { \
|
||||
.command = IOSAV_ACT, \
|
||||
.ranksel_ap = 1, \
|
||||
}, \
|
||||
.subseq_ctrl = { \
|
||||
.cmd_executions = 4, \
|
||||
.cmd_delay_gap = 8, \
|
||||
.post_ssq_wait = 40, \
|
||||
.data_direction = SSQ_NA, \
|
||||
}, \
|
||||
.sp_cmd_addr = { \
|
||||
.address = 0, \
|
||||
.rowbits = 6, \
|
||||
.bank = 0, \
|
||||
.rank = slotrank, \
|
||||
}, \
|
||||
.addr_update = { \
|
||||
.inc_bank = 1, \
|
||||
.addr_wrap = 18, \
|
||||
}, \
|
||||
}, \
|
||||
/* DRAM command WR */ \
|
||||
[1] = { \
|
||||
.sp_cmd_ctrl = { \
|
||||
.command = IOSAV_WR, \
|
||||
.ranksel_ap = 1, \
|
||||
}, \
|
||||
.subseq_ctrl = { \
|
||||
.cmd_executions = 100, \
|
||||
.cmd_delay_gap = 4, \
|
||||
.post_ssq_wait = 40, \
|
||||
.data_direction = SSQ_WR, \
|
||||
}, \
|
||||
.sp_cmd_addr = { \
|
||||
.address = 0, \
|
||||
.rowbits = 0, \
|
||||
.bank = 0, \
|
||||
.rank = slotrank, \
|
||||
}, \
|
||||
.addr_update = { \
|
||||
.inc_addr_8 = 1, \
|
||||
.addr_wrap = 18, \
|
||||
}, \
|
||||
}, \
|
||||
/* DRAM command RD */ \
|
||||
[2] = { \
|
||||
.sp_cmd_ctrl = { \
|
||||
.command = IOSAV_RD, \
|
||||
.ranksel_ap = 1, \
|
||||
}, \
|
||||
.subseq_ctrl = { \
|
||||
.cmd_executions = 100, \
|
||||
.cmd_delay_gap = 4, \
|
||||
.post_ssq_wait = 40, \
|
||||
.data_direction = SSQ_RD, \
|
||||
}, \
|
||||
.sp_cmd_addr = { \
|
||||
.address = 0, \
|
||||
.rowbits = 0, \
|
||||
.bank = 0, \
|
||||
.rank = slotrank, \
|
||||
}, \
|
||||
.addr_update = { \
|
||||
.inc_addr_8 = 1, \
|
||||
.addr_wrap = 18, \
|
||||
}, \
|
||||
}, \
|
||||
/* DRAM command PRE */ \
|
||||
[3] = { \
|
||||
.sp_cmd_ctrl = { \
|
||||
.command = IOSAV_PRE, \
|
||||
.ranksel_ap = 1, \
|
||||
}, \
|
||||
.subseq_ctrl = { \
|
||||
.cmd_executions = 1, \
|
||||
.cmd_delay_gap = 3, \
|
||||
.post_ssq_wait = 40, \
|
||||
.data_direction = SSQ_NA, \
|
||||
}, \
|
||||
.sp_cmd_addr = { \
|
||||
.address = 1024, \
|
||||
.rowbits = 6, \
|
||||
.bank = 0, \
|
||||
.rank = slotrank, \
|
||||
}, \
|
||||
.addr_update = { \
|
||||
.addr_wrap = 18, \
|
||||
}, \
|
||||
}, \
|
||||
}
|
||||
|
||||
void iosav_write_sequence(const int ch, const struct iosav_ssq *seq, const unsigned int length);
|
||||
void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer);
|
||||
void iosav_run_once(const int ch);
|
||||
|
|
|
|||
Loading…
Reference in New Issue