mb/system76/addw1: Add System76 Adder Workstation 1
Change-Id: I5dd3bc320ca640728e1d86180c6bfa0dc7295760 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Tim Crawford
Felix Held
parent
5ab146674c
commit
6a93a45242
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@ -180,6 +180,7 @@ The boards in this section are not real mainboards, but emulators.
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## System76
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- [Adder Workstation 1](system76/addw1.md)
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- [Darter Pro 6](system76/darp6.md)
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- [Darter Pro 7](system76/darp7.md)
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- [Galago Pro 4](system76/galp4.md)
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@ -0,0 +1,67 @@
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# System76 Adder Workstation 1 (addw1)
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## Specs
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- CPU
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- Intel Core i7-9750H
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- Intel Core i9-9980HK
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- Chipset
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- Intel HM370
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- EC
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- ITE IT8587E running [System76 EC](https://github.com/system76/ec)
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- Graphics
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- Intel UHD Graphics 630
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- NVIDIA GeForce RTX 2070
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- eDP 15.6" 3840x2160 OLED (Samsung ATNA56WR06)
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- 1x HDMI
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- 1x Mini DisplayPort 1.3
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- 1x DisplayPort 1.3 over USB-C
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- Memory:
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- Up to 64GB dual-channel DDR4 @ 2666 MHz, or
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- Up to 32GB dual-channel DDR4 @ 3000 MHz
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- Networking
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- Gigabit Ethernet
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- Intel Wireless-AC
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- Power
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- 230W (19.5V, 11.8A) AC adapter
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- Removable 62Wh 6-cell battery
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- Sound
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- Realtek ALC1220 codec
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- TAS5825MRHBR smart AMP
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- Internal speakers and microphone
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- Combined headphone and microphone 3.5mm jack
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- Combined microphone and S/PDIF 3.5mm jack
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- HDMI, Mini DisplayPort, USB-C DP audio
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- Storage
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- M.2 PCIe/SATA SSD1
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- M.2 PCIe/SATA SSD2
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- 2.5" SATA HDD/SSD
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- RTS5250 SD card reader
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- USB
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- 1x USB Type-C with Thunderbolt 3
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- 1x USB 3.1 Gen2 Type-C
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- 3x USB 3.1 Gen1 Type-A
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## Flashing coreboot
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```eval_rst
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+---------------------+---------------------+
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| Type | Value |
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+=====================+=====================+
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| Socketed flash | no |
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+---------------------+---------------------+
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| Vendor | Macronix |
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+---------------------+---------------------+
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| Model | MX25L12873F |
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+---------------------+---------------------+
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| Size | 16 MiB |
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+---------------------+---------------------+
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| Package | SOIC-8 |
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+---------------------+---------------------+
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| Internal flashing | yes |
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+---------------------+---------------------+
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| External flashing | yes |
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+---------------------+---------------------+
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```
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The flash chip (U61) is next to the battery connector.
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@ -0,0 +1,65 @@
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if BOARD_SYSTEM76_ADDW1
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_HID
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select DRIVERS_I2C_TAS5825M
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select EC_SYSTEM76_EC
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select EC_SYSTEM76_EC_BAT_THRESHOLDS
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select EC_SYSTEM76_EC_COLOR_KEYBOARD
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select EC_SYSTEM76_EC_OLED
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM2
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select NO_UART_ON_SUPERIO
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select PCIEXP_HOTPLUG
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select SOC_INTEL_CANNONLAKE_PCH_H
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select SOC_INTEL_COFFEELAKE if BOARD_SYSTEM76_ADDW1
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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select TPM_RDRESP_NEED_DELAY
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config MAINBOARD_DIR
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default "system76/addw1"
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config VARIANT_DIR
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default "addw1" if BOARD_SYSTEM76_ADDW1
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config MAINBOARD_PART_NUMBER
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default "addw1" if BOARD_SYSTEM76_ADDW1
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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default "Adder WS"
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config MAINBOARD_VERSION
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default "addw1" if BOARD_SYSTEM76_ADDW1
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config CBFS_SIZE
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default 0xA00000
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config CONSOLE_POST
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default y
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config ONBOARD_VGA_IS_PRIMARY
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default y
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config UART_FOR_CONSOLE
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default 2
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config DIMM_MAX
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default 2
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config POST_DEVICE
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default n
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endif
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@ -0,0 +1,2 @@
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config BOARD_SYSTEM76_ADDW1
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bool "addw1"
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@ -0,0 +1,11 @@
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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bootblock-y += bootblock.c
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bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
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romstage-y += romstage.c
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ramstage-y += ramstage.c
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ramstage-y += variants/$(VARIANT_DIR)/gpio.c
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ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
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ramstage-y += variants/$(VARIANT_DIR)/tas5825m.c
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@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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// GPP_K6 SCI
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Method (_L06, 0, Serialized) {
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Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
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If (\_SB.PCI0.LPCB.EC0.ECOK) {
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If (\_SB.PCI0.LPCB.EC0.WFNO == 1) {
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Notify(\_SB.LID0, 0x80)
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}
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}
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}
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@ -0,0 +1,13 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#define EC_GPE_SCI 0x03 /* GPP_K3 */
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#define EC_GPE_SWI 0x06 /* GPP_K6 */
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#include <ec/system76/ec/acpi/ec.asl>
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Scope (\_SB) {
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#include "sleep.asl"
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}
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Scope (\_GPE) {
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#include "gpe.asl"
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}
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@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Method called from _PTS prior to enter sleep state */
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Method (MPTS, 1) {
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\_SB.PCI0.LPCB.EC0.PTS (Arg0)
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}
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/* Method called from _WAK prior to wakeup */
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Method (MWAK, 1) {
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\_SB.PCI0.LPCB.EC0.WAK (Arg0)
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}
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@ -0,0 +1,6 @@
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Vendor name: System76
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Category: laptop
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <variant/gpio.h>
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void bootblock_mainboard_early_init(void)
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{
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variant_configure_early_gpios();
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}
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@ -0,0 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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power_on_after_fail=Enable
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@ -0,0 +1,39 @@
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# SPDX-License-Identifier: GPL-2.0-only
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entries
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0 384 r 0 reserved_memory
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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# RTC_CLK_ALTCENTURY
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400 8 r 0 century
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409 2 e 7 power_on_after_fail
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412 4 e 6 debug_level
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984 16 h 0 check_sum
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enumerations
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4 0 Fallback
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4 1 Normal
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6 0 Emergency
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6 1 Alert
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6 2 Critical
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6 3 Error
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6 4 Warning
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6 5 Notice
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6 6 Info
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6 7 Debug
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6 8 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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checksums
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checksum 408 983 984
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@ -0,0 +1,205 @@
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chip soc/intel/cannonlake
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register "common_soc_config" = "{
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// Touchpad I2C bus
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 80,
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.fall_time_ns = 110,
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},
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}"
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# CPU (soc/intel/cannonlake/cpu.c)
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# Power limit
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register "power_limits_config" = "{
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.tdp_pl1_override = 45,
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.tdp_pl2_override = 90,
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}"
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# Enable Enhanced Intel SpeedStep
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register "eist_enable" = "1"
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# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
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register "enable_c6dram" = "1"
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# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
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# Misc
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register "AcousticNoiseMitigation" = "1"
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# Power
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register "PchPmSlpS3MinAssert" = "3" # 50ms
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register "PchPmSlpS4MinAssert" = "1" # 1s
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register "PchPmSlpSusMinAssert" = "4" # 4s
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register "PchPmSlpAMinAssert" = "4" # 2s
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# Thermal
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register "tcc_offset" = "8"
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# Serial IRQ Continuous
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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# PM Util (soc/intel/cannonlake/pmutil.c)
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "PMC_GPP_K"
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register "gpe0_dw1" = "PMC_GPP_G"
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register "gpe0_dw2" = "PMC_GPP_E"
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# Actual device tree
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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subsystemid 0x1558 0x65d1 inherit
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device pci 00.0 on end # Host Bridge
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device pci 01.0 on # GPU Port
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# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
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register "PcieClkSrcUsage[8]" = "0x40"
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register "PcieClkSrcClkReq[8]" = "8"
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end
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 on # SA Thermal device
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register "Device4Enable" = "1"
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end
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device pci 12.0 on end # Thermal Subsystem
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device pci 12.5 off end # UFS SCS
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device pci 12.6 off end # GSPI #2
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device pci 13.0 off end # Integrated Sensor Hub
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device pci 14.0 on # USB xHCI
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 2
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 audio
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 back
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key RGB keyboard
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register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Camera
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register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 right
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 audio
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 back
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end
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device pci 14.2 on end # Shared SRAM
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device pci 14.3 on # CNVi wifi
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chip drivers/wifi/generic
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register "wake" = "PME_B0_EN_BIT"
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device generic 0 on end
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end
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end
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device pci 14.5 off end # SDCard
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device pci 15.0 on end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 17.0 on # SATA
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register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
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register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A)
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end
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device pci 19.2 off end # UART #2
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device pci 1a.0 off end # eMMC
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device pci 1b.0 on # PCI Express Port 17
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# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
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register "PcieRpEnable[16]" = "1"
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register "PcieRpLtrEnable[16]" = "1"
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register "PcieRpHotPlug[16]" = "1"
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register "PcieClkSrcUsage[0]" = "16"
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register "PcieClkSrcClkReq[0]" = "0"
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end
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device pci 1b.1 off end # PCI Express Port 18
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device pci 1b.2 off end # PCI Express Port 19
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device pci 1b.3 off end # PCI Express Port 20
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device pci 1b.4 on # PCI Express Port 21
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# PCI Express root port #21 x4, Clock 10 (SSD2)
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register "PcieRpEnable[20]" = "1"
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register "PcieRpLtrEnable[20]" = "1"
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register "PcieClkSrcUsage[10]" = "20"
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register "PcieClkSrcClkReq[10]" = "10"
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register "PcieRpSlotImplemented[20]" = "1"
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end
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device pci 1b.5 off end # PCI Express Port 22
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device pci 1b.6 off end # PCI Express Port 23
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device pci 1b.7 off end # PCI Express Port 24
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device pci 1c.0 off end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 on # PCI Express Port 9
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# PCI Express root port #9 x4, Clock 9 (SSD1)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[9]" = "8"
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register "PcieClkSrcClkReq[9]" = "9"
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register "PcieRpSlotImplemented[8]" = "1"
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end
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1d.4 off end # PCI Express Port 13
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device pci 1d.5 on # PCI Express Port 14
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# PCI Express root port #14 x1, Clock 5 (GLAN)
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register "PcieRpEnable[13]" = "1"
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register "PcieRpLtrEnable[13]" = "1"
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register "PcieClkSrcUsage[5]" = "13"
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register "PcieClkSrcClkReq[5]" = "5"
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register "PcieRpSlotImplemented[13]" = "1"
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end
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device pci 1d.6 on # PCI Express Port 15
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# PCI Express root port #15 x1, Clock 7 (Card Reader)
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register "PcieRpEnable[14]" = "1"
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register "PcieRpLtrEnable[14]" = "1"
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register "PcieClkSrcUsage[7]" = "14"
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register "PcieClkSrcClkReq[7]" = "7"
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register "PcieRpSlotImplemented[14]" = "1"
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end
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device pci 1d.7 on # PCI Express Port 16
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# PCI Express root port #16 x1, Clock 6 (WLAN)
|
||||
register "PcieRpEnable[15]" = "1"
|
||||
register "PcieRpLtrEnable[15]" = "1"
|
||||
register "PcieClkSrcUsage[6]" = "15"
|
||||
register "PcieClkSrcClkReq[6]" = "6"
|
||||
register "PcieRpSlotImplemented[15]" = "1"
|
||||
end
|
||||
device pci 1e.0 off end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1f.0 on # LPC Interface
|
||||
register "gen1_dec" = "0x00040069"
|
||||
register "gen2_dec" = "0x00fc0e01"
|
||||
register "gen3_dec" = "0x00fc0f01"
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 off end # P2SB
|
||||
device pci 1f.2 hidden end # Power Management Controller
|
||||
device pci 1f.3 on # Intel HDA
|
||||
register "PchHdaAudioLinkHda" = "1"
|
||||
end
|
||||
device pci 1f.4 on # SMBus
|
||||
chip drivers/i2c/tas5825m
|
||||
register "id" = "0"
|
||||
device i2c 4e on end # (8bit address: 0x9c)
|
||||
end
|
||||
end
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20110725
|
||||
)
|
||||
{
|
||||
#include <acpi/dsdt_top.asl>
|
||||
#include <soc/intel/common/block/acpi/acpi/platform.asl>
|
||||
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Device (\_SB.PCI0) {
|
||||
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
|
||||
#include <soc/intel/cannonlake/acpi/southbridge.asl>
|
||||
}
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
Scope (\_SB.PCI0.LPCB) {
|
||||
#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
}
|
||||
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
void variant_configure_early_gpios(void);
|
||||
void variant_configure_gpios(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/device.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
static void mainboard_init(void *chip_info)
|
||||
{
|
||||
variant_configure_gpios();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.init = mainboard_init,
|
||||
};
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/cnl_memcfg_init.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct cnl_mb_cfg memcfg = {
|
||||
.spd[0] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xa0},
|
||||
},
|
||||
.spd[2] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xa4},
|
||||
},
|
||||
.rcomp_resistor = { 121, 75, 100 },
|
||||
.rcomp_targets = { 50, 25, 20, 20, 26 },
|
||||
.dq_pins_interleaved = 1,
|
||||
.vref_ca_config = 2,
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
// Allow higher memory speeds
|
||||
memupd->FspmConfig.SaOcSupport = 1;
|
||||
|
||||
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
|
||||
}
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
Board name: addw1
|
||||
Release year: 2019
|
||||
Binary file not shown.
|
|
@ -0,0 +1,264 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/gpio.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* ------- GPIO Group GPD ------- */
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW#
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
|
||||
PAD_NC(GPD2, NONE),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
|
||||
PAD_NC(GPD6, NONE),
|
||||
PAD_NC(GPD7, NONE),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
|
||||
PAD_NC(GPD9, NONE),
|
||||
PAD_NC(GPD10, NONE),
|
||||
PAD_NC(GPD11, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_A ------- */
|
||||
PAD_CFG_GPO(GPP_A0, 0, DEEP), // SB_KBCRST#
|
||||
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
|
||||
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
|
||||
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
|
||||
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
|
||||
PAD_CFG_GPI(GPP_A7, NONE, DEEP), // SCI#_GPP_A7
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // ECCLKRUN#
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC
|
||||
PAD_NC(GPP_A10, DN_20K),
|
||||
PAD_NC(GPP_A11, UP_20K),
|
||||
PAD_NC(GPP_A12, NONE),
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK#
|
||||
PAD_NC(GPP_A16, DN_20K),
|
||||
PAD_CFG_GPI(GPP_A17, NONE, DEEP), // AMP_TYPE_DET
|
||||
PAD_CFG_GPO(GPP_A18, 1, DEEP), // SB_BLON
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
PAD_CFG_GPO(GPP_A20, 1, DEEP), // PEX_WAKE#
|
||||
PAD_NC(GPP_A21, NONE),
|
||||
PAD_CFG_GPO(GPP_A22, 1, DEEP), // SMARTAMP_SW
|
||||
PAD_CFG_GPI(GPP_A23, NONE, DEEP), // SMART AMP PWR (L:3.3VS H:3.3V)
|
||||
|
||||
/* ------- GPIO Group GPP_B ------- */
|
||||
PAD_CFG_GPI(GPP_B0, NONE, DEEP), // TPM_PIRQ#
|
||||
PAD_NC(GPP_B1, NONE),
|
||||
PAD_NC(GPP_B2, NONE),
|
||||
// PCH_GPP_B3 (touchpad interrupt)
|
||||
PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT),
|
||||
PAD_NC(GPP_B4, NONE),
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // TBT_CLKREQ#
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
PAD_NC(GPP_B7, NONE),
|
||||
PAD_NC(GPP_B8, NONE),
|
||||
PAD_NC(GPP_B9, NONE),
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // GLAN_CLKREQ#
|
||||
PAD_NC(GPP_B11, NONE),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
|
||||
_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000), // PLT_RST#
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
|
||||
PAD_NC(GPP_B15, NONE),
|
||||
PAD_NC(GPP_B16, NONE),
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT STRAP
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
PAD_CFG_GPI(GPP_B20, NONE, DEEP), // SMI#_GPP_B20
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP), // BOOT BIOS STRAP
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP), // DCI-OOB STRAP
|
||||
|
||||
/* ------- GPIO Group GPP_C ------- */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
|
||||
_PAD_CFG_STRUCT(GPP_C2, 0x40880100, 0x0000), // CNVI_WAKE#
|
||||
PAD_NC(GPP_C3, NONE),
|
||||
PAD_NC(GPP_C4, NONE),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP), // WLAN_WAKEUP#
|
||||
PAD_NC(GPP_C6, NONE),
|
||||
PAD_NC(GPP_C7, NONE),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID2
|
||||
PAD_CFG_GPI(GPP_C10, NONE, DEEP), // BOARD_ID1
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP), // TBT_DET#
|
||||
PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH
|
||||
PAD_CFG_GPI(GPP_C13, NONE, DEEP), // TPM_DET
|
||||
PAD_CFG_GPO(GPP_C14, 1, DEEP), // GPU_EVENT#
|
||||
PAD_CFG_GPI(GPP_C15, NONE, DEEP), // 100K pull-down
|
||||
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // TP_DAT_PCH_I2C0
|
||||
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // TP_CLK_PCH_I2C0
|
||||
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C1_SDA
|
||||
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // I2C1_SCL
|
||||
//PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
|
||||
//PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
|
||||
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), // UART2_RTS#
|
||||
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), // UART2_CTS#
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
PAD_NC(GPP_D0, NONE),
|
||||
PAD_NC(GPP_D1, NONE),
|
||||
PAD_NC(GPP_D2, NONE),
|
||||
PAD_NC(GPP_D3, NONE),
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RST#
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // CNVI_CLKREQ
|
||||
PAD_NC(GPP_D7, NONE),
|
||||
PAD_NC(GPP_D8, NONE),
|
||||
PAD_NC(GPP_D9, NONE),
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
PAD_NC(GPP_D11, NONE),
|
||||
PAD_NC(GPP_D12, NONE),
|
||||
PAD_NC(GPP_D13, NONE),
|
||||
PAD_NC(GPP_D14, NONE),
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
PAD_NC(GPP_D17, NONE),
|
||||
PAD_NC(GPP_D18, NONE),
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
PAD_NC(GPP_D20, NONE),
|
||||
PAD_NC(GPP_D21, NONE),
|
||||
PAD_NC(GPP_D22, NONE),
|
||||
PAD_NC(GPP_D23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
PAD_NC(GPP_E0, NONE),
|
||||
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
|
||||
PAD_NC(GPP_E2, NONE),
|
||||
PAD_NC(GPP_E3, NONE),
|
||||
PAD_NC(GPP_E4, NONE),
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // SATA_DEVSLP1
|
||||
PAD_CFG_GPO(GPP_E6, 1, DEEP), // PCH_MUTE#
|
||||
PAD_NC(GPP_E7, NONE),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATAHDD_LED#
|
||||
PAD_NC(GPP_E9, NONE),
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_F ------- */
|
||||
PAD_NC(GPP_F0, NONE),
|
||||
PAD_NC(GPP_F1, NONE),
|
||||
PAD_NC(GPP_F2, NONE),
|
||||
PAD_CFG_GPO(GPP_F3, 1, DEEP), // GPP_F3_LAN_RST#
|
||||
PAD_CFG_GPO(GPP_F4, 1, DEEP), // GPP_F4_TBT_RST#
|
||||
PAD_NC(GPP_F5, NONE),
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
PAD_NC(GPP_F7, NONE),
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
PAD_CFG_GPO(GPP_F9, 0, DEEP), // PS8331_SW
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS RECOVERY ENABLE STRAP
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP), // H_SKTOCC_N
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
PAD_NC(GPP_F17, NONE),
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
|
||||
//PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
|
||||
//PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
|
||||
|
||||
/* ------- GPIO Group GPP_G ------- */
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP), // GSYNC_DET
|
||||
PAD_NC(GPP_G1, NONE), // test point
|
||||
PAD_CFG_GPI(GPP_G2, NONE, DEEP), // NVSR_DET#
|
||||
PAD_NC(GPP_G3, NONE),
|
||||
PAD_NC(GPP_G4, NONE),
|
||||
PAD_NC(GPP_G5, NONE),
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP), // SWI#_GPP_G6
|
||||
PAD_NC(GPP_G7, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_H ------- */
|
||||
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // SD4.0_CLKREQ#
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // SSD1_CLKREQ#
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD2_CLKREQ#
|
||||
PAD_NC(GPP_H5, NONE),
|
||||
PAD_CFG_GPO(GPP_H6, 1, DEEP), // PCIE_SSD1_RST#
|
||||
PAD_CFG_GPO(GPP_H7, 1, DEEP), // PCIE_SSD2_RST#
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP), // GPP_H8_LAN_RST#
|
||||
PAD_CFG_GPI(GPP_H9, NONE, DEEP), // TBT_GPIO_WAKE#
|
||||
PAD_NC(GPP_H10, NONE),
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP), // ESPI FLASH SHARING STRAP
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP), // TBTA_HRESET
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, DEEP), // RESERVED STRAP
|
||||
_PAD_CFG_STRUCT(GPP_H16, 0x44000101, 0x0000), // TBT_RTD3_PWR_EN
|
||||
PAD_CFG_GPO(GPP_H17, 0, PLTRST), // TBT_FORCE_PWR
|
||||
PAD_NC(GPP_H18, NONE),
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP), // XTAL FREQUENCY SELECT STRAP
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT#
|
||||
|
||||
/* ------- GPIO Group GPP_I ------- */
|
||||
PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), // ANX7411_HPD
|
||||
PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // HDMI_HPD
|
||||
PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // MDP_E_HPD
|
||||
PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), // MDP_A_TBT_HPD
|
||||
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // SB_IEDP_HPD
|
||||
PAD_CFG_GPO(GPP_I5, 1, DEEP), // TBT_GPIO_RST#
|
||||
PAD_NC(GPP_I6, NONE),
|
||||
PAD_NC(GPP_I7, NONE),
|
||||
PAD_CFG_GPO(GPP_I8, 1, DEEP), // SSD1_PWR_EN
|
||||
PAD_CFG_GPO(GPP_I9, 1, DEEP), // SSD2_PWR_EN
|
||||
PAD_NC(GPP_I10, NONE),
|
||||
PAD_NC(GPP_I11, NONE),
|
||||
PAD_CFG_GPO(GPP_I12, 1, DEEP), // SATA_PWR_EN
|
||||
PAD_NC(GPP_I13, NONE),
|
||||
PAD_NC(GPP_I14, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_J ------- */
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
|
||||
PAD_CFG_GPO(GPP_J1, 1, DEEP), // GPP_J1
|
||||
PAD_NC(GPP_J2, NONE),
|
||||
PAD_NC(GPP_J3, NONE),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
|
||||
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
|
||||
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
|
||||
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
|
||||
PAD_NC(GPP_J10, NONE),
|
||||
PAD_NC(GPP_J11, DN_20K),
|
||||
|
||||
/* ------- GPIO Group GPP_K ------- */
|
||||
PAD_CFG_GPO(GPP_K0, 0, DEEP), // GPP_K0_SPK_MUTE
|
||||
PAD_CFG_GPO(GPP_K1, 0, DEEP), // GPP_K1_WOOFER_MUTE
|
||||
PAD_NC(GPP_K2, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000), // SCI#_GPP_K3
|
||||
PAD_NC(GPP_K4, NONE),
|
||||
PAD_NC(GPP_K5, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#_GPP_K6
|
||||
PAD_CFG_GPI(GPP_K7, NONE, DEEP), // GPP_K7_LAN_WAKEUP#
|
||||
PAD_CFG_GPO(GPP_K8, 1, DEEP), // GPP_K8_LAN_RTD3
|
||||
PAD_NC(GPP_K9, NONE),
|
||||
PAD_NC(GPP_K10, NONE),
|
||||
PAD_NC(GPP_K11, NONE),
|
||||
PAD_CFG_GPO(GPP_K12, 1, DEEP), // PCH_GPP_K12
|
||||
PAD_NC(GPP_K13, NONE),
|
||||
PAD_CFG_GPO(GPP_K14, 0, DEEP), // GPP_K14_TEST_R
|
||||
_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000), // GPP_K15_INTP_OUT
|
||||
PAD_NC(GPP_K16, NONE),
|
||||
PAD_NC(GPP_K17, NONE),
|
||||
PAD_CFG_GPO(GPP_K18, 1, DEEP), // GPP_K18_TBT_WAKE#
|
||||
_PAD_CFG_STRUCT(GPP_K19, 0x42800101, 0x0000), // SMI#_GPP_K19
|
||||
PAD_NC(GPP_K20, NONE),
|
||||
PAD_NC(GPP_K21, NONE),
|
||||
PAD_NC(GPP_K22, NONE),
|
||||
PAD_NC(GPP_K23, NONE),
|
||||
};
|
||||
|
||||
void variant_configure_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/gpio.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
|
||||
PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
|
||||
PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
|
||||
};
|
||||
|
||||
void variant_configure_early_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x155865d1, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155865d1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130), // DMIC
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f), // FRONT (Port-D)
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000), // SURR (Port-A)
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0), // CENTER/LFE (Port-G)
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0), // SIDE (Port-H)
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040), // MIC1 (Port-B)
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0), // MIC2 (Port-F)
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), // LINE1 (Port-C)
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110), // LINE2 (Port-E)
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), // PCBEEP
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150), // S/PDIF-OUT
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
// Enable DMIC microphone on ALC1220
|
||||
0x02050036,
|
||||
0x02042a6a,
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
chip soc/intel/cannonlake
|
||||
# Serial I/O
|
||||
register "SerialIoDevMode" = "{
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
|
||||
[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x65d1 inherit
|
||||
device pci 15.0 on # I2C #0
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""PNP0C50""
|
||||
register "generic.desc" = ""Synaptics Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
|
||||
register "generic.probed" = "1"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 2c on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue