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purism/librem13v1, librem13v2, liberm15v3: Fix EC LPC I/O port 

The LPC I/O ports for EC communication were not set properly,
causing ectool to fail to read the Index I/O from the EC.

The EC Index I/O is on port 0x380 and the LPC I/O port needs to be
decoded by the PCI device for it to be accessible.

Correct the value for the Librem 13v1, 13v2 and 15v3.

Change-Id: Ide1d158340eadfabbce5f70ceccddfabb4db188a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Youness Alaoui 2018-03-13 16:53:30 -04:00 committed by Patrick Georgi
parent 7a2cf65032
commit 6aa28d93b3
3 changed files with 10 additions and 6 deletions
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4
src/mainboard/purism/librem13v1/devicetree.cb
View File

@ -18,6 +18,10 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
# EC host command ranges are in 0x380-0x383 & 0x80-0x8f
register "gen1_dec" = "0x00000381"
register "gen2_dec" = "0x000c0081"
# Port 0 is HDD # Port 0 is HDD
# Port 3 is M.2 NGFF # Port 3 is M.2 NGFF
register "sata_port_map" = "0x9" register "sata_port_map" = "0x9"

6
src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
View File

@ -15,9 +15,9 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D" register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E" register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f # EC host command ranges are in 0x380-0x383 & 0x80-0x8f
register "gen1_dec" = "0x00fc0801" register "gen1_dec" = "0x00000381"
register "gen2_dec" = "0x000c0201" register "gen2_dec" = "0x000c0081"
# Enable "Intel Speed Shift Technology" # Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1" register "speed_shift_enable" = "1"

6
src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
View File

@ -15,9 +15,9 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D" register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E" register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f # EC host command ranges are in 0x380-0x383 & 0x80-0x8f
register "gen1_dec" = "0x00fc0801" register "gen1_dec" = "0x00000381"
register "gen2_dec" = "0x000c0201" register "gen2_dec" = "0x000c0081"
# Enable "Intel Speed Shift Technology" # Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1" register "speed_shift_enable" = "1"