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emulation/qemu-q35: Enable ECAM earlier 

Align implementation with real hardwares, such that ECAM
(PCI configuration via MMIO) is available for use when
console is initialised.

Change-Id: I288991f31d3f1678132aa4315168c09eabbbe98d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76206
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Kyösti Mälkki 2023-07-04 09:22:39 +03:00 committed by Felix Held
parent cde4f3b279
commit 6aaa4f9198
1 changed files with 4 additions and 5 deletions
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9
src/mainboard/emulation/qemu-q35/bootblock.c
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@ -7,7 +7,7 @@
#include "q35.h" #include "q35.h"
static void bootblock_northbridge_init(void) void bootblock_soc_early_init(void)
{ {
/* /*
* The "io" variant of the config access is explicitly used to * The "io" variant of the config access is explicitly used to
@ -24,9 +24,6 @@ static void bootblock_northbridge_init(void)
const uint32_t pciexbar = make_pciexbar(); const uint32_t pciexbar = make_pciexbar();
pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_HI, 0); pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_HI, 0);
pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, pciexbar); pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, pciexbar);
if (CONFIG(BOOTBLOCK_CONSOLE))
mainboard_machine_check();
} }
static void bootblock_southbridge_init(void) static void bootblock_southbridge_init(void)
@ -40,6 +37,8 @@ static void bootblock_southbridge_init(void)
void bootblock_soc_init(void) void bootblock_soc_init(void)
{ {
bootblock_northbridge_init(); if (CONFIG(BOOTBLOCK_CONSOLE))
mainboard_machine_check();
bootblock_southbridge_init(); bootblock_southbridge_init();
} }