get config tool satisfied.. let's see if we get this working..
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
257a58b60d
commit
6ac60f8dfe
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@ -1,86 +1,3 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HAVE_OPTION_TABLE
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uses USE_OPTION_TABLE
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uses CONFIG_ROM_STREAM
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uses IRQ_SLOT_COUNT
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uses MAINBOARD
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uses ARCH
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uses FALLBACK_SIZE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses HAVE_MP_TABLE
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE = 256*1024
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###
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### Build options
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###
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## no MP table
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##
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default HAVE_MP_TABLE=0
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=5
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object irq_tables.o
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=1
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###
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### LinuxBIOS layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 65536
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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default HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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default USE_OPTION_TABLE = 0
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##
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##
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## Compute the location and size of where this firmware image
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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@ -97,9 +14,8 @@ end
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## Compute the start location and size size of
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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## The linuxBIOS bootloader.
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##
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default CONFIG_ROM_STREAM = 1
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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##
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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## Compute where this copy of linuxBIOS will start in the boot rom
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@ -126,8 +42,8 @@ arch i386 end
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## Build the objects we have code for in this directory.
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## Build the objects we have code for in this directory.
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##
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##
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driver mainboard.o
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driver mainboard.o
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#object reset.o
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#object reset.o
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##
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##
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@ -145,30 +61,30 @@ end
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makerule ./auto.E
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -E -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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end
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makerule ./auto.inc
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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end
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##
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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##
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/i386/entry32.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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##
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if USE_FALLBACK_IMAGE
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset16.inc
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/i386/reset16.lds
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ldscript /cpu/x86/16bit/reset16.lds
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else
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else
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mainboardinit cpu/i386/reset32.inc
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/i386/reset32.lds
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ldscript /cpu/x86/32bit/reset32.lds
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end
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end
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### Should this be in the northbridge code?
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### Should this be in the northbridge code?
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@ -180,11 +96,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
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mainboardinit arch/i386/lib/id.inc
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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ldscript /arch/i386/lib/id.lds
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##
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## Setup our mtrrs
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##
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# mainboardinit cpu/p6/earlymtrr.inc
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###
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###
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### This is the early phase of linuxBIOS startup
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### Things are delicate and we test to see if we should
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##
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##
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## Setup RAM
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## Setup RAM
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##
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit ./auto.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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##
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##
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## Include the secondary Configuration files
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## Include the secondary Configuration files
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@ -211,13 +125,18 @@ dir /pc80
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config chip.h
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config chip.h
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chip northbridge/amd/sc520
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chip northbridge/amd/sc520
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chip southbridge amd/sc520
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device pci_domain 0 on
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register "enable_usb" = "0"
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device pci 0.0 on
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register "enable_native_ide" = "1"
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#chip southbridge/amd/sc520
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register "enable_com_ports" = "1"
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# register "enable_usb" = "0"
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register "enable_keyboard" = "0"
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# register "enable_native_ide" = "1"
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register "enable_nvram" = "1"
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# register "enable_com_ports" = "1"
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end
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# register "enable_keyboard" = "0"
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chip cpu/amd/sc520
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# register "enable_nvram" = "1"
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end
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# end
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end
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chip cpu/amd/sc520
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end
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end
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end
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end
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@ -0,0 +1,105 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HAVE_OPTION_TABLE
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uses USE_OPTION_TABLE
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uses CONFIG_ROM_STREAM
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uses IRQ_SLOT_COUNT
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uses MAINBOARD
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PART_NUMBER
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uses LINUXBIOS_EXTRA_VERSION
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uses ARCH
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uses FALLBACK_SIZE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses _RAMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses HAVE_MP_TABLE
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uses HAVE_ACPI_TABLES
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE = 256*1024
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###
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### Build options
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###
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## no MP table
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##
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default HAVE_MP_TABLE=0
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=5
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=1
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###
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### LinuxBIOS layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 65536
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default FALLBACK_SIZE = 131072
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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default HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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default USE_OPTION_TABLE = 0
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default _RAMBASE = 0x00004000
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default CONFIG_ROM_STREAM = 1
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##
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## The default compiler
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##
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default CROSS_COMPILE=""
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default CC="$(CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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end
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