AGESA: Remove separate f15rl
Change-Id: I18c62ad034249c5ad14e5d5e708b4f0d4bcbf400 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kyösti Mälkki
parent
3754cda835
commit
6acaca7e40
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@ -19,7 +19,6 @@ config CPU_AMD_AGESA
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default y if CPU_AMD_AGESA_FAMILY14
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default y if CPU_AMD_AGESA_FAMILY14
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default y if CPU_AMD_AGESA_FAMILY15
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default y if CPU_AMD_AGESA_FAMILY15
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default y if CPU_AMD_AGESA_FAMILY15_TN
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default y if CPU_AMD_AGESA_FAMILY15_TN
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default y if CPU_AMD_AGESA_FAMILY15_RL
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default y if CPU_AMD_AGESA_FAMILY16_KB
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default y if CPU_AMD_AGESA_FAMILY16_KB
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default n
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default n
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_BOOTBLOCK_X86_32
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@ -85,5 +84,4 @@ source src/cpu/amd/agesa/family12/Kconfig
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source src/cpu/amd/agesa/family14/Kconfig
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source src/cpu/amd/agesa/family14/Kconfig
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source src/cpu/amd/agesa/family15/Kconfig
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source src/cpu/amd/agesa/family15/Kconfig
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source src/cpu/amd/agesa/family15tn/Kconfig
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source src/cpu/amd/agesa/family15tn/Kconfig
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source src/cpu/amd/agesa/family15rl/Kconfig
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source src/cpu/amd/agesa/family16kb/Kconfig
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source src/cpu/amd/agesa/family16kb/Kconfig
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@ -16,7 +16,6 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) += family15rl
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
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romstage-y += s3_resume.c
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romstage-y += s3_resume.c
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@ -1,39 +0,0 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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# Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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config CPU_AMD_AGESA_FAMILY15_RL
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bool
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select X86_AMD_FIXED_MTRRS
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if CPU_AMD_AGESA_FAMILY15_RL
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config CPU_ADDR_BITS
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int
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default 48
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config CBB
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hex
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default 0x0
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config CDB
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hex
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default 0x18
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config XIP_ROM_SIZE
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hex
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default 0x100000
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endif # CPU_AMD_AGESA_FAMILY15_RL
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@ -1,32 +0,0 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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romstage-y += fixme.c
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romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
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ramstage-y += fixme.c
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ramstage-y += chip_name.c
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ramstage-y += model_15_init.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
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subdirs-y += ../../mtrr
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subdirs-y += ../../smm
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subdirs-y += ../../../x86/tsc
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subdirs-y += ../../../x86/lapic
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subdirs-y += ../../../x86/cache
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subdirs-y += ../../../x86/mtrr
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subdirs-y += ../../../x86/pae
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subdirs-y += ../../../x86/smm
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@ -1,78 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Sage Electronic Engineering, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Processor Object
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*
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*/
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Scope (\_PR) { /* define processor scope */
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Processor(
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P000, /* name space name */
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0, /* Unique number for this processor */
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0x810, /* PBLK system I/O address !hardcoded! */
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0x06 /* PBLKLEN for boot processor */
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) {
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}
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Processor(
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P001, /* name space name */
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1, /* Unique number for this processor */
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0x0810, /* PBLK system I/O address !hardcoded! */
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0x06 /* PBLKLEN for boot processor */
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) {
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}
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Processor(
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P002, /* name space name */
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2, /* Unique number for this processor */
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0x0810, /* PBLK system I/O address !hardcoded! */
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0x06 /* PBLKLEN for boot processor */
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) {
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}
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Processor(
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P003, /* name space name */
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3, /* Unique number for this processor */
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0x0810, /* PBLK system I/O address !hardcoded! */
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0x06 /* PBLKLEN for boot processor */
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) {
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}
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Processor(
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P004, /* name space name */
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4, /* Unique number for this processor */
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0x0810, /* PBLK system I/O address !hardcoded! */
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0x06 /* PBLKLEN for boot processor */
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) {
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}
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Processor(
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P005, /* name space name */
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5, /* Unique number for this processor */
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0x0810, /* PBLK system I/O address !hardcoded! */
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0x06 /* PBLKLEN for boot processor */
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) {
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}
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Processor(
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P006, /* name space name */
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6, /* Unique number for this processor */
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0x0810, /* PBLK system I/O address !hardcoded! */
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0x06 /* PBLKLEN for boot processor */
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) {
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}
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Processor(
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P007, /* name space name */
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7, /* Unique number for this processor */
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0x0810, /* PBLK system I/O address !hardcoded! */
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0x06 /* PBLKLEN for boot processor */
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) {
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}
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} /* End _PR scope */
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@ -1,21 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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struct chip_operations cpu_amd_agesa_family15rl_ops = {
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CHIP_NAME("AMD CPU Family 15h Model 10h-1Fh")
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};
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@ -1,81 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/mtrr.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <AGESA.h>
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#include "amdlib.h"
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void amd_initcpuio(void)
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{
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UINT64 MsrReg;
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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/* Enable legacy video routing: D18F1xF4 VGA Enable */
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
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PciData = 1;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* The platform BIOS needs to ensure the memory ranges of Hudson legacy
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* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
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* set to non-posted regions.
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*/
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
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PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
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PciData |= 1 << 7; /* set NP (non-posted) bit */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
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PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Map the remaining PCI hole as posted MMIO */
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
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PciData = 0x00FECF00; /* last address before non-posted range */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
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PciData = (UINT32)MsrReg;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Send all IO (0000-FFFF) to southbridge. */
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
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PciData = 0x0000F000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
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PciData = 0x00000003;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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}
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void amd_initmmio(void)
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{
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UINT64 MsrReg;
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AMD_CONFIG_PARAMS StdHeader;
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/*
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Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
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Address MSR register.
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*/
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MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
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LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
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/* Set ROM cache onto WP to decrease post time */
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MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
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LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
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MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
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LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
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}
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@ -1,140 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/smm.h>
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#include <cpu/amd/mtrr.h>
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#include <device/device.h>
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#include <string.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/pae.h>
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#include <pc80/mc146818rtc.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/amdfam15.h>
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#include <arch/acpi.h>
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#include <cpu/amd/agesa/s3_resume.h>
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static void model_15_init(device_t dev)
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{
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printk(BIOS_DEBUG, "Model 15 Init.\n");
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u8 i;
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msr_t msr;
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int msrno;
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unsigned int cpu_idx;
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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u32 siblings;
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#endif
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//x86_enable_cache();
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amd_setup_mtrrs();
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//x86_mtrr_check();
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disable_cache ();
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/* Enable access to AMD RdDram and WrDram extension bits */
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msr = rdmsr(SYSCFG_MSR);
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msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
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msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
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wrmsr(SYSCFG_MSR, msr);
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// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
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msr.lo = msr.hi = 0;
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wrmsr (0x259, msr);
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msr.lo = msr.hi = 0x1e1e1e1e;
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||||||
wrmsr(0x250, msr);
|
|
||||||
wrmsr(0x258, msr);
|
|
||||||
for (msrno = 0x268; msrno <= 0x26f; msrno++)
|
|
||||||
wrmsr (msrno, msr);
|
|
||||||
|
|
||||||
msr = rdmsr(SYSCFG_MSR);
|
|
||||||
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
|
|
||||||
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
|
|
||||||
wrmsr(SYSCFG_MSR, msr);
|
|
||||||
|
|
||||||
if (acpi_is_wakeup())
|
|
||||||
restore_mtrr();
|
|
||||||
|
|
||||||
x86_mtrr_check();
|
|
||||||
x86_enable_cache();
|
|
||||||
|
|
||||||
/* zero the machine check error status registers */
|
|
||||||
msr.lo = 0;
|
|
||||||
msr.hi = 0;
|
|
||||||
for (i = 0; i < 6; i++) {
|
|
||||||
wrmsr(MCI_STATUS + (i * 4), msr);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Enable the local CPU APICs */
|
|
||||||
setup_lapic();
|
|
||||||
|
|
||||||
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
|
|
||||||
siblings = cpuid_ecx(0x80000008) & 0xff;
|
|
||||||
|
|
||||||
if (siblings > 0) {
|
|
||||||
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
|
|
||||||
msr.lo |= 1 << 28;
|
|
||||||
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
|
|
||||||
|
|
||||||
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
|
|
||||||
msr.hi |= 1 << (33 - 32);
|
|
||||||
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
|
|
||||||
}
|
|
||||||
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* DisableCf8ExtCfg */
|
|
||||||
msr = rdmsr(NB_CFG_MSR);
|
|
||||||
msr.hi &= ~(1 << (46 - 32));
|
|
||||||
wrmsr(NB_CFG_MSR, msr);
|
|
||||||
|
|
||||||
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
|
|
||||||
cpu_idx = cpu_info()->index;
|
|
||||||
printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
|
|
||||||
|
|
||||||
/* Set SMM base address for this CPU */
|
|
||||||
msr = rdmsr(MSR_SMM_BASE);
|
|
||||||
msr.lo = SMM_BASE - (cpu_idx * 0x400);
|
|
||||||
wrmsr(MSR_SMM_BASE, msr);
|
|
||||||
|
|
||||||
/* Enable the SMM memory window */
|
|
||||||
msr = rdmsr(MSR_SMM_MASK);
|
|
||||||
msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
|
|
||||||
wrmsr(MSR_SMM_MASK, msr);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Write protect SMM space with SMMLOCK. */
|
|
||||||
msr = rdmsr(HWCR_MSR);
|
|
||||||
msr.lo |= (1 << 0);
|
|
||||||
wrmsr(HWCR_MSR, msr);
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct device_operations cpu_dev_ops = {
|
|
||||||
.init = model_15_init,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct cpu_device_id cpu_table[] = {
|
|
||||||
{ X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 */
|
|
||||||
{ 0, 0 },
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct cpu_driver model_15 __cpu_driver = {
|
|
||||||
.ops = &cpu_dev_ops,
|
|
||||||
.id_table = cpu_table,
|
|
||||||
};
|
|
||||||
|
|
@ -1,61 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
|
||||||
* Copyright (C) 2017 Kyösti Mälkki
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <console/console.h>
|
|
||||||
#include <cpu/amd/car.h>
|
|
||||||
|
|
||||||
#include <northbridge/amd/agesa/agesawrapper.h>
|
|
||||||
#include <northbridge/amd/agesa/state_machine.h>
|
|
||||||
#include <northbridge/amd/agesa/agesa_helper.h>
|
|
||||||
|
|
||||||
void agesa_main(struct sysinfo *cb)
|
|
||||||
{
|
|
||||||
post_code(0x37);
|
|
||||||
agesawrapper_amdinitreset();
|
|
||||||
|
|
||||||
post_code(0x39);
|
|
||||||
agesawrapper_amdinitearly();
|
|
||||||
|
|
||||||
if (!cb->s3resume) {
|
|
||||||
printk(BIOS_INFO, "Normal boot\n");
|
|
||||||
|
|
||||||
post_code(0x40);
|
|
||||||
agesawrapper_amdinitpost();
|
|
||||||
} else {
|
|
||||||
printk(BIOS_INFO, "S3 detected\n");
|
|
||||||
|
|
||||||
post_code(0x60);
|
|
||||||
agesawrapper_amdinitresume();
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
void agesa_postcar(struct sysinfo *cb)
|
|
||||||
{
|
|
||||||
if (!cb->s3resume) {
|
|
||||||
printk(BIOS_INFO, "Normal boot postcar\n");
|
|
||||||
|
|
||||||
post_code(0x41);
|
|
||||||
agesawrapper_amdinitenv();
|
|
||||||
} else {
|
|
||||||
printk(BIOS_INFO, "S3 resume postcar\n");
|
|
||||||
|
|
||||||
post_code(0x61);
|
|
||||||
amd_initcpuio();
|
|
||||||
|
|
||||||
post_code(0x62);
|
|
||||||
agesawrapper_amds3laterestore();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,58 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License or (at your option)
|
|
||||||
* any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* udelay() impementation for SMI handlers
|
|
||||||
* This is neat in that it never writes to hardware registers, and thus does not
|
|
||||||
* modify the state of the hardware while servicing SMIs.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <cpu/x86/msr.h>
|
|
||||||
#include <cpu/x86/tsc.h>
|
|
||||||
#include <delay.h>
|
|
||||||
#include <stdint.h>
|
|
||||||
|
|
||||||
void udelay(uint32_t us)
|
|
||||||
{
|
|
||||||
uint8_t fid, did, pstate_idx;
|
|
||||||
uint64_t tsc_clock, tsc_start, tsc_now, tsc_wait_ticks;
|
|
||||||
msr_t msr;
|
|
||||||
const uint64_t tsc_base = 100000000;
|
|
||||||
|
|
||||||
/* Get initial timestamp before we do the math */
|
|
||||||
tsc_start = rdtscll();
|
|
||||||
|
|
||||||
/* Get the P-state. This determines which MSR to read */
|
|
||||||
msr = rdmsr(0xc0010063);
|
|
||||||
pstate_idx = msr.lo & 0x07;
|
|
||||||
|
|
||||||
/* Get FID and VID for current P-State */
|
|
||||||
msr = rdmsr(0xc0010064 + pstate_idx);
|
|
||||||
|
|
||||||
/* Extract the FID and VID values */
|
|
||||||
fid = msr.lo & 0x3f;
|
|
||||||
did = (msr.lo >> 6) & 0x7;
|
|
||||||
|
|
||||||
/* Calculate the CPU clock (from base freq of 100MHz) */
|
|
||||||
tsc_clock = tsc_base * (fid + 0x10) / (1 << did);
|
|
||||||
|
|
||||||
/* Now go on and wait */
|
|
||||||
tsc_wait_ticks = (tsc_clock / 1000000) * us;
|
|
||||||
|
|
||||||
do {
|
|
||||||
tsc_now = rdtscll();
|
|
||||||
} while (tsc_now - tsc_wait_ticks < tsc_start);
|
|
||||||
}
|
|
||||||
|
|
@ -141,8 +141,7 @@ untampered_lapic:
|
||||||
/* This is an ugly hack, and we should find a way to read the CPU index
|
/* This is an ugly hack, and we should find a way to read the CPU index
|
||||||
* without relying on the LAPIC ID.
|
* without relying on the LAPIC ID.
|
||||||
*/
|
*/
|
||||||
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) \
|
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN)
|
||||||
|| IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL)
|
|
||||||
/* LAPIC IDs start from 0x10; map that to the proper core index */
|
/* LAPIC IDs start from 0x10; map that to the proper core index */
|
||||||
subl $0x10, %ecx
|
subl $0x10, %ecx
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -19,7 +19,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12
|
||||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14
|
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14
|
||||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15
|
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15
|
||||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn
|
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn
|
||||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_RL) += family15rl
|
|
||||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb
|
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb
|
||||||
|
|
||||||
romstage-y += def_callouts.c eventlog.c
|
romstage-y += def_callouts.c eventlog.c
|
||||||
|
|
|
||||||
|
|
@ -285,7 +285,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
|
||||||
AmdParamStruct.StdHeader.Func = 0;
|
AmdParamStruct.StdHeader.Func = 0;
|
||||||
AmdParamStruct.StdHeader.ImageBasePtr = 0;
|
AmdParamStruct.StdHeader.ImageBasePtr = 0;
|
||||||
|
|
||||||
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) || \
|
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) || \
|
||||||
IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY16_KB)
|
IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY16_KB)
|
||||||
AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
|
AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,36 +0,0 @@
|
||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
config NORTHBRIDGE_AMD_AGESA_FAMILY15_RL
|
|
||||||
bool
|
|
||||||
|
|
||||||
if NORTHBRIDGE_AMD_AGESA_FAMILY15_RL
|
|
||||||
|
|
||||||
config HW_MEM_HOLE_SIZEK
|
|
||||||
hex
|
|
||||||
default 0x100000
|
|
||||||
|
|
||||||
config HW_MEM_HOLE_SIZE_AUTO_INC
|
|
||||||
bool
|
|
||||||
default n
|
|
||||||
|
|
||||||
config MMCONF_BASE_ADDRESS
|
|
||||||
hex
|
|
||||||
default 0xF8000000
|
|
||||||
|
|
||||||
config MMCONF_BUS_NUMBER
|
|
||||||
int
|
|
||||||
default 64
|
|
||||||
|
|
||||||
endif # NORTHBRIDGE_AMD_AGESA_FAMILY15_RL
|
|
||||||
|
|
@ -1,24 +0,0 @@
|
||||||
#
|
|
||||||
# This file is part of the coreboot project.
|
|
||||||
#
|
|
||||||
# Copyright (C) 2012 Advanced Micro Devices, Inc.
|
|
||||||
#
|
|
||||||
# This program is free software; you can redistribute it and/or modify
|
|
||||||
# it under the terms of the GNU General Public License as published by
|
|
||||||
# the Free Software Foundation; version 2 of the License.
|
|
||||||
#
|
|
||||||
# This program is distributed in the hope that it will be useful,
|
|
||||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
# GNU General Public License for more details.
|
|
||||||
#
|
|
||||||
|
|
||||||
romstage-y += dimmSpd.c
|
|
||||||
|
|
||||||
ramstage-y += iommu.c
|
|
||||||
ramstage-y += northbridge.c
|
|
||||||
|
|
||||||
ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
|
|
||||||
romstage-y += ../family15tn/state_machine.c
|
|
||||||
ramstage-y += ../family15tn/state_machine.c
|
|
||||||
endif
|
|
||||||
|
|
@ -1,96 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Note: Only need HID on Primary Bus */
|
|
||||||
External (TOM1)
|
|
||||||
External (TOM2)
|
|
||||||
Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */
|
|
||||||
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
|
|
||||||
|
|
||||||
/* Describe the Northbridge devices */
|
|
||||||
|
|
||||||
Method (_BBN, 0, NotSerialized)
|
|
||||||
{
|
|
||||||
Return (Zero)
|
|
||||||
}
|
|
||||||
|
|
||||||
Method (_STA, 0, NotSerialized)
|
|
||||||
{
|
|
||||||
Return (0x0B)
|
|
||||||
}
|
|
||||||
|
|
||||||
Method (_PRT, 0, NotSerialized)
|
|
||||||
{
|
|
||||||
If (PMOD)
|
|
||||||
{
|
|
||||||
Return (APR0)
|
|
||||||
}
|
|
||||||
|
|
||||||
Return (PR0)
|
|
||||||
}
|
|
||||||
|
|
||||||
Device(AMRT) {
|
|
||||||
Name(_ADR, 0x00000000)
|
|
||||||
} /* end AMRT */
|
|
||||||
|
|
||||||
/* Dev2 is also an external GFX bridge */
|
|
||||||
Device(PBR2) {
|
|
||||||
Name(_ADR, 0x00020000)
|
|
||||||
Name(_PRW, Package() {0x18, 4})
|
|
||||||
Method(_PRT,0) {
|
|
||||||
If(PMOD) { Return(APS2) } /* APIC mode */
|
|
||||||
Return (PS2) /* PIC Mode */
|
|
||||||
} /* end _PRT */
|
|
||||||
} /* end PBR2 */
|
|
||||||
|
|
||||||
/* Dev4 GPP0 Root Port Bridge */
|
|
||||||
Device(PBR4) {
|
|
||||||
Name(_ADR, 0x00040000)
|
|
||||||
Name(_PRW, Package() {0x18, 4})
|
|
||||||
Method(_PRT,0) {
|
|
||||||
If(PMOD) { Return(APS4) } /* APIC mode */
|
|
||||||
Return (PS4) /* PIC Mode */
|
|
||||||
} /* end _PRT */
|
|
||||||
} /* end PBR4 */
|
|
||||||
|
|
||||||
/* Dev5 GPP1 Root Port Bridge */
|
|
||||||
Device(PBR5) {
|
|
||||||
Name(_ADR, 0x00050000)
|
|
||||||
Name(_PRW, Package() {0x18, 4})
|
|
||||||
Method(_PRT,0) {
|
|
||||||
If(PMOD) { Return(APS5) } /* APIC mode */
|
|
||||||
Return (PS5) /* PIC Mode */
|
|
||||||
} /* end _PRT */
|
|
||||||
} /* end PBR5 */
|
|
||||||
|
|
||||||
/* Dev6 GPP2 Root Port Bridge */
|
|
||||||
Device(PBR6) {
|
|
||||||
Name(_ADR, 0x00060000)
|
|
||||||
Name(_PRW, Package() {0x18, 4})
|
|
||||||
Method(_PRT,0) {
|
|
||||||
If(PMOD) { Return(APS6) } /* APIC mode */
|
|
||||||
Return (PS6) /* PIC Mode */
|
|
||||||
} /* end _PRT */
|
|
||||||
} /* end PBR6 */
|
|
||||||
|
|
||||||
/* The onboard EtherNet chip */
|
|
||||||
Device(PBR7) {
|
|
||||||
Name(_ADR, 0x00070000)
|
|
||||||
Name(_PRW, Package() {0x18, 4})
|
|
||||||
Method(_PRT,0) {
|
|
||||||
If(PMOD) { Return(APS7) } /* APIC mode */
|
|
||||||
Return (PS7) /* PIC Mode */
|
|
||||||
} /* end _PRT */
|
|
||||||
} /* end PBR7 */
|
|
||||||
|
|
@ -1,24 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _NB_AGESA_CHIP_H_
|
|
||||||
#define _NB_AGESA_CHIP_H_
|
|
||||||
|
|
||||||
struct northbridge_amd_agesa_family15rl_config
|
|
||||||
{
|
|
||||||
u8 spdAddrLookup[2][2][4];
|
|
||||||
};
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,62 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
|
||||||
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <device/pci_def.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <stdlib.h>
|
|
||||||
|
|
||||||
/* warning: Porting.h includes an open #pragma pack(1) */
|
|
||||||
#include "Porting.h"
|
|
||||||
#include "AGESA.h"
|
|
||||||
#include "amdlib.h"
|
|
||||||
#include "chip.h"
|
|
||||||
|
|
||||||
#include <northbridge/amd/agesa/dimmSpd.h>
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Gets the SMBus address for an SPD from the array in devicetree.cb
|
|
||||||
* then read the SPD into the supplied buffer.
|
|
||||||
*/
|
|
||||||
AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info)
|
|
||||||
{
|
|
||||||
UINT8 spdAddress;
|
|
||||||
|
|
||||||
DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
|
|
||||||
if (dev == NULL)
|
|
||||||
return AGESA_ERROR;
|
|
||||||
|
|
||||||
DEVTREE_CONST struct northbridge_amd_agesa_family15rl_config *config = dev->chip_info;
|
|
||||||
if (config == NULL)
|
|
||||||
return AGESA_ERROR;
|
|
||||||
|
|
||||||
if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup))
|
|
||||||
return AGESA_ERROR;
|
|
||||||
if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0]))
|
|
||||||
return AGESA_ERROR;
|
|
||||||
if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0]))
|
|
||||||
return AGESA_ERROR;
|
|
||||||
|
|
||||||
spdAddress = config->spdAddrLookup
|
|
||||||
[info->SocketId][info->MemChannelId][info->DimmId];
|
|
||||||
|
|
||||||
if (spdAddress == 0)
|
|
||||||
return AGESA_ERROR;
|
|
||||||
|
|
||||||
int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128);
|
|
||||||
if (err)
|
|
||||||
return AGESA_ERROR;
|
|
||||||
return AGESA_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
@ -1,69 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Rudolf Marek <r.marek@assembler.cz>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <device/pci.h>
|
|
||||||
#include <device/pci_ids.h>
|
|
||||||
#include <device/pci_ops.h>
|
|
||||||
#include <lib.h>
|
|
||||||
|
|
||||||
static void iommu_read_resources(device_t dev)
|
|
||||||
{
|
|
||||||
struct resource *res;
|
|
||||||
|
|
||||||
/* Get the normal pci resources of this device */
|
|
||||||
pci_dev_read_resources(dev);
|
|
||||||
|
|
||||||
/* Add an extra subtractive resource for both memory and I/O. */
|
|
||||||
res = new_resource(dev, 0x44);
|
|
||||||
res->size = 512 * 1024;
|
|
||||||
res->align = log2(res->size);
|
|
||||||
res->gran = log2(res->size);
|
|
||||||
res->limit = 0xffffffff; /* 4G */
|
|
||||||
res->flags = IORESOURCE_MEM;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void iommu_set_resources(device_t dev)
|
|
||||||
{
|
|
||||||
struct resource *res;
|
|
||||||
|
|
||||||
pci_dev_set_resources(dev);
|
|
||||||
|
|
||||||
res = find_resource(dev, 0x44);
|
|
||||||
/* Remember this resource has been stored */
|
|
||||||
res->flags |= IORESOURCE_STORED;
|
|
||||||
/* For now, do only 32-bit space allocation */
|
|
||||||
pci_write_config32(dev, 0x48, 0x0);
|
|
||||||
pci_write_config32(dev, 0x44, res->base | (1 << 0));
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct pci_operations lops_pci = {
|
|
||||||
.set_subsystem = pci_dev_set_subsystem,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct device_operations iommu_ops = {
|
|
||||||
.read_resources = iommu_read_resources,
|
|
||||||
.set_resources = iommu_set_resources,
|
|
||||||
.enable_resources = pci_dev_enable_resources,
|
|
||||||
.init = 0,
|
|
||||||
.scan_bus = 0,
|
|
||||||
.ops_pci = &lops_pci,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct pci_driver iommu_driver __pci_driver = {
|
|
||||||
.ops = &iommu_ops,
|
|
||||||
.vendor = PCI_VENDOR_ID_AMD,
|
|
||||||
.device = PCI_DEVICE_ID_AMD_15H_NB_IOMMU,
|
|
||||||
};
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -2,7 +2,6 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += f12
|
||||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14
|
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14
|
||||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += f15
|
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += f15
|
||||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += f15tn
|
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += f15tn
|
||||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) += f15tn
|
|
||||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += f16kb
|
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += f16kb
|
||||||
|
|
||||||
ifeq ($(CONFIG_CPU_AMD_AGESA),y)
|
ifeq ($(CONFIG_CPU_AMD_AGESA),y)
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue