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mb/**/acpi: Remove unused files 

Remove commented-out entries in dsdt.asl, and then remove files that do
not get built.

Change-Id: I579e7ffbc2d6596fd7ffe6863ff3b3fb14b0ade6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2019-12-19 23:22:21 +01:00 committed by Nico Huber
parent e3d9d67e99
commit 6ad0ab1a69
28 changed files with 0 additions and 537 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/asus/p5gc-mx/acpi/thermal.asl
View File

@ -1 +0,0 @@
/* dummy */

8
src/mainboard/asus/p5gc-mx/dsdt.asl
View File

@ -23,21 +23,13 @@ DefinitionBlock(
0x20090419 // OEM revision 0x20090419 // OEM revision
) )
{ {
/* #include "acpi/platform.asl" */
// global NVS and variables // global NVS and variables
#include <southbridge/intel/i82801gx/acpi/globalnvs.asl> #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
#include <southbridge/intel/common/acpi/platform.asl> #include <southbridge/intel/common/acpi/platform.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
// mainboard specific devices // mainboard specific devices
#include "acpi/mainboard.asl" #include "acpi/mainboard.asl"
// Thermal Zone
//#include "acpi/thermal.asl"
#include <cpu/intel/speedstep/acpi/cpu.asl> #include <cpu/intel/speedstep/acpi/cpu.asl>
Scope (\_SB) { Scope (\_SB) {

1
src/mainboard/gigabyte/ga-945gcm-s2l/acpi/thermal.asl
View File

@ -1 +0,0 @@
/* dummy */

6
src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl
View File

@ -29,15 +29,9 @@ DefinitionBlock(
#include <southbridge/intel/i82801gx/acpi/globalnvs.asl> #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
#include <southbridge/intel/common/acpi/platform.asl> #include <southbridge/intel/common/acpi/platform.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
// mainboard specific devices // mainboard specific devices
#include "acpi/mainboard.asl" #include "acpi/mainboard.asl"
// Thermal Zone
//#include "acpi/thermal.asl"
#include <cpu/intel/speedstep/acpi/cpu.asl> #include <cpu/intel/speedstep/acpi/cpu.asl>
Scope (\_SB) { Scope (\_SB) {

3
src/mainboard/google/auron/dsdt.asl
View File

@ -32,9 +32,6 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <soc/intel/broadwell/acpi/globalnvs.asl> #include <soc/intel/broadwell/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
// CPU // CPU
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>

3
src/mainboard/google/butterfly/dsdt.asl
View File

@ -35,9 +35,6 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) { Scope (\_SB) {

3
src/mainboard/google/jecht/dsdt.asl
View File

@ -33,9 +33,6 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <soc/intel/broadwell/acpi/globalnvs.asl> #include <soc/intel/broadwell/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
// CPU // CPU
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>

64
src/mainboard/google/link/acpi/ivybridge_pci_irqs.asl
View File

@ -1,64 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* This is board specific information: IRQ routing for IvyBridge */
// PCI Interrupt Routing
Method(_PRT)
{
If (PICM) {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, 0, 16 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, 0, 22 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, 0, 19 },
Package() { 0x001cffff, 1, 0, 20 },
Package() { 0x001cffff, 2, 0, 17 },
Package() { 0x001cffff, 3, 0, 18 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, 0, 19 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, 0, 20 },
// LPC devices 0:1f.0
Package() { 0x001fffff, 0, 0, 21 },
Package() { 0x001fffff, 1, 0, 22 },
Package() { 0x001fffff, 2, 0, 23 },
Package() { 0x001fffff, 3, 0, 16 },
})
} Else {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
})
}
}

4
src/mainboard/google/link/dsdt.asl
View File

@ -35,10 +35,6 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) { Scope (\_SB) {

64
src/mainboard/google/parrot/acpi/ivybridge_pci_irqs.asl
View File

@ -1,64 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* This is board specific information: IRQ routing for IvyBridge */
// PCI Interrupt Routing
Method(_PRT)
{
If (PICM) {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, 0, 16 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, 0, 22 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, 0, 19 },
Package() { 0x001cffff, 1, 0, 20 },
Package() { 0x001cffff, 2, 0, 17 },
Package() { 0x001cffff, 3, 0, 18 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, 0, 19 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, 0, 20 },
// LPC devices 0:1f.0
Package() { 0x001fffff, 0, 0, 21 },
Package() { 0x001fffff, 1, 0, 22 },
Package() { 0x001fffff, 2, 0, 23 },
Package() { 0x001fffff, 3, 0, 16 },
})
} Else {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
})
}
}

3
src/mainboard/google/parrot/dsdt.asl
View File

@ -34,9 +34,6 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) { Scope (\_SB) {

3
src/mainboard/google/slippy/dsdt.asl
View File

@ -32,9 +32,6 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
// CPU // CPU
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>

3
src/mainboard/google/stout/dsdt.asl
View File

@ -36,9 +36,6 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) { Scope (\_SB) {

89
src/mainboard/ibase/mb899/acpi/thermal.asl
View File

@ -1,89 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// Thermal Zone
Scope (\_TZ)
{
ThermalZone (THRM)
{
// FIXME these could/should be read from the
// GNVS area, so they can be controlled by
// coreboot
Name(TC1V, 0x04)
Name(TC2V, 0x03)
Name(TSPV, 0x64)
// At which temperature should the OS start
// active cooling?
Method (_AC0, 0, Serialized)
{
Return (0xf5c) // Value for Rocky
}
// Method (_AC1, 0, Serialized)
// {
// Return (0xf5c)
// }
// Critical shutdown temperature
Method (_CRT, 0, Serialized)
{
Return (Add (0x0aac, 0x50)) // FIXME
}
// CPU throttling start temperature
Method (_PSV, 0, Serialized)
{
Return (0xaaf) // FIXME
}
// Get DTS Temperature
Method (_TMP, 0, Serialized)
{
Return (0xaac) // FIXME
}
// Processors used for active cooling
Method (_PSL, 0, Serialized)
{
If (MPEN) {
Return (Package() {\_PR.CP01, \_PR.CP02})
}
Return (Package() {\_PR.CP01})
}
// TC1 value for passive cooling
Method (_TC1, 0, Serialized)
{
Return (TC1V)
}
// TC2 value for passive cooling
Method (_TC2, 0, Serialized)
{
Return (TC2V)
}
// Sampling period for passive cooling
Method (_TSP, 0, Serialized)
{
Return (TSPV)
}
}
}

5
src/mainboard/ibase/mb899/dsdt.asl
View File

@ -30,11 +30,6 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/platform.asl> #include <southbridge/intel/common/acpi/platform.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
//#include "acpi/thermal.asl"
#include <cpu/intel/speedstep/acpi/cpu.asl> #include <cpu/intel/speedstep/acpi/cpu.asl>
Scope (\_SB) { Scope (\_SB) {

3
src/mainboard/intel/baskingridge/dsdt.asl
View File

@ -31,9 +31,6 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
#include "acpi/thermal.asl" #include "acpi/thermal.asl"
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>

89
src/mainboard/intel/d945gclf/acpi/thermal.asl
View File

@ -1,89 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// Thermal Zone
Scope (\_TZ)
{
ThermalZone (THRM)
{
// FIXME these could/should be read from the
// GNVS area, so they can be controlled by
// coreboot
Name(TC1V, 0x04)
Name(TC2V, 0x03)
Name(TSPV, 0x64)
// At which temperature should the OS start
// active cooling?
Method (_AC0, 0, Serialized)
{
Return (0xf5c) // Value for Rocky
}
// Method (_AC1, 0, Serialized)
// {
// Return (0xf5c)
// }
// Critical shutdown temperature
Method (_CRT, 0, Serialized)
{
Return (Add (0x0aac, 0x50)) // FIXME
}
// CPU throttling start temperature
Method (_PSV, 0, Serialized)
{
Return (0xaaf) // FIXME
}
// Get DTS Temperature
Method (_TMP, 0, Serialized)
{
Return (0xaac) // FIXME
}
// Processors used for active cooling
Method (_PSL, 0, Serialized)
{
If (MPEN) {
Return (Package() {\_PR.CP01, \_PR.CP02})
}
Return (Package() {\_PR.CP01})
}
// TC1 value for passive cooling
Method (_TC1, 0, Serialized)
{
Return (TC1V)
}
// TC2 value for passive cooling
Method (_TC2, 0, Serialized)
{
Return (TC2V)
}
// Sampling period for passive cooling
Method (_TSP, 0, Serialized)
{
Return (TSPV)
}
}
}

6
src/mainboard/intel/d945gclf/dsdt.asl
View File

@ -29,15 +29,9 @@ DefinitionBlock(
#include <southbridge/intel/i82801gx/acpi/globalnvs.asl> #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
#include <southbridge/intel/common/acpi/platform.asl> #include <southbridge/intel/common/acpi/platform.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
// mainboard specific devices // mainboard specific devices
#include "acpi/mainboard.asl" #include "acpi/mainboard.asl"
// Thermal Zone
//#include "acpi/thermal.asl"
#include <cpu/intel/speedstep/acpi/cpu.asl> #include <cpu/intel/speedstep/acpi/cpu.asl>
Scope (\_SB) { Scope (\_SB) {

64
src/mainboard/intel/emeraldlake2/acpi/ivybridge_pci_irqs.asl
View File

@ -1,64 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* This is board specific information: IRQ routing for IvyBridge */
// PCI Interrupt Routing
Method(_PRT)
{
If (PICM) {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, 0, 16 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, 0, 22 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, 0, 17 },
Package() { 0x001cffff, 1, 0, 18 },
Package() { 0x001cffff, 2, 0, 19 },
Package() { 0x001cffff, 3, 0, 20 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, 0, 19 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, 0, 20 },
// LPC devices 0:1f.0
Package() { 0x001fffff, 0, 0, 21 },
Package() { 0x001fffff, 1, 0, 22 },
Package() { 0x001fffff, 2, 0, 23 },
Package() { 0x001fffff, 3, 0, 16 },
})
} Else {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
})
}
}

3
src/mainboard/intel/emeraldlake2/dsdt.asl
View File

@ -34,9 +34,6 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) { Scope (\_SB) {

3
src/mainboard/intel/harcuvar/dsdt.asl
View File

@ -30,9 +30,6 @@ DefinitionBlock(
#include "acpi/platform.asl" #include "acpi/platform.asl"
#include "acpi/mainboard.asl" #include "acpi/mainboard.asl"
// General Purpose Events
//#include "acpi/gpe.asl"
// Thermal Handler // Thermal Handler
#include "acpi/thermal.asl" #include "acpi/thermal.asl"

3
src/mainboard/intel/wtm2/dsdt.asl
View File

@ -33,9 +33,6 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <soc/intel/broadwell/acpi/globalnvs.asl> #include <soc/intel/broadwell/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
// CPU // CPU
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>

89
src/mainboard/kontron/986lcd-m/acpi/thermal.asl
View File

@ -1,89 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// Thermal Zone
Scope (\_TZ)
{
ThermalZone (THRM)
{
// FIXME these could/should be read from the
// GNVS area, so they can be controlled by
// coreboot
Name(TC1V, 0x04)
Name(TC2V, 0x03)
Name(TSPV, 0x64)
// At which temperature should the OS start
// active cooling?
Method (_AC0, 0, Serialized)
{
Return (0xf5c) // Value for Rocky
}
// Method (_AC1, 0, Serialized)
// {
// Return (0xf5c)
// }
// Critical shutdown temperature
Method (_CRT, 0, Serialized)
{
Return (Add (0x0aac, 0x50)) // FIXME
}
// CPU throttling start temperature
Method (_PSV, 0, Serialized)
{
Return (0xaaf) // FIXME
}
// Get DTS Temperature
Method (_TMP, 0, Serialized)
{
Return (0xaac) // FIXME
}
// Processors used for active cooling
Method (_PSL, 0, Serialized)
{
If (MPEN) {
Return (Package() {\_PR.CP01, \_PR.CP02})
}
Return (Package() {\_PR.CP01})
}
// TC1 value for passive cooling
Method (_TC1, 0, Serialized)
{
Return (TC1V)
}
// TC2 value for passive cooling
Method (_TC2, 0, Serialized)
{
Return (TC2V)
}
// Sampling period for passive cooling
Method (_TSP, 0, Serialized)
{
Return (TSPV)
}
}
}

5
src/mainboard/kontron/986lcd-m/dsdt.asl
View File

@ -29,11 +29,6 @@ DefinitionBlock(
#include <southbridge/intel/i82801gx/acpi/globalnvs.asl> #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
#include <southbridge/intel/common/acpi/platform.asl> #include <southbridge/intel/common/acpi/platform.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
//#include "acpi/thermal.asl"
#include <cpu/intel/speedstep/acpi/cpu.asl> #include <cpu/intel/speedstep/acpi/cpu.asl>
Scope (\_SB) { Scope (\_SB) {

3
src/mainboard/kontron/ktqm77/dsdt.asl
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@ -35,9 +35,6 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) { Scope (\_SB) {

3
src/mainboard/samsung/lumpy/dsdt.asl
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@ -34,9 +34,6 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) { Scope (\_SB) {

3
src/mainboard/samsung/stumpy/dsdt.asl
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@ -32,9 +32,6 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
#include "acpi/thermal.asl" #include "acpi/thermal.asl"
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>

3
src/mainboard/scaleway/tagada/dsdt.asl
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@ -30,9 +30,6 @@ DefinitionBlock(
#include "acpi/platform.asl" #include "acpi/platform.asl"
#include "acpi/mainboard.asl" #include "acpi/mainboard.asl"
// General Purpose Events
//#include "acpi/gpe.asl"
// Thermal Handler // Thermal Handler
#include "acpi/thermal.asl" #include "acpi/thermal.asl"