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src/soc/tigerlake: Update SerialIoDebugMode UPD in FSP-M 

Due to refactoring of Serial IO code in FSP v3163 onwards we need to
set SerialIoUartDebugMode UPD in FSP-M to SkipInit so that SerialIoUart
initialization is skipped in FSP. This makes sure that SerialIo
initialization in coreboot is not changed by FSP.

BUG=b:155315876
BRANCH=none
TEST=build and boot tglrvp/ripto/volteer and check UART debug logs

Cq-Depend: chrome-internal:2944102
Cq-Depend: chrome-internal:2939733
Cq-Depend: chrome-internal:2943140
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I8ba4b9015fa25a84b6b99419ce4d413c9d9daa44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40899
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Srinidhi N Kaushik 2020-04-29 19:49:25 -07:00 committed by Stefan Reinauer
parent e7a083ec3d
commit 6ad8352a3d
1 changed files with 1 additions and 0 deletions
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1
src/soc/intel/tigerlake/romstage/fsp_params.c
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@ -82,6 +82,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
} }
m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit;
/* ISH */ /* ISH */
dev = pcidev_path_on_root(PCH_DEVFN_ISH); dev = pcidev_path_on_root(PCH_DEVFN_ISH);