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Revert "soc/qualcomm: Update the wait time for checking PCIe link up" 

This reverts commit 4b5ba94363.

Reason for revert: This optimization is causing the non-serial enabled
tot BIOS to not boot.  To get tot back into good shape, will revert
for now and reevalute this fix and resubmit at a later time.

BUG=b:218406702
BRANCH=None

TEST=reboot from AP console (on herobrine) after flashing
     image-herobrine.bin.
     prior to fix the device would never boot to login prompt.
     after rever the device would boot to login prompt again.

Change-Id: Iaac5f2fb2120f6aa41a0ce9a763d50fd7b9a3ec7
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
This commit is contained in:
Shelley Chen 2022-10-12 17:48:47 +00:00
parent d91f3a4eaf
commit 6ae4d2e0a6
1 changed files with 2 additions and 2 deletions
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4
src/soc/qualcomm/common/include/soc/pcie.h
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@ -48,8 +48,8 @@
#define LINK_SPEED_GEN_1 0x1 #define LINK_SPEED_GEN_1 0x1
#define LINK_SPEED_GEN_2 0x2 #define LINK_SPEED_GEN_2 0x2
#define LINK_SPEED_GEN_3 0x3 #define LINK_SPEED_GEN_3 0x3
#define PCIE_LINK_UP_MS 10 #define PCIE_LINK_UP_MS 100
#define LINK_WAIT_MAX_RETRIES 100 #define LINK_WAIT_MAX_RETRIES 10
#define COMMAND_MASK 0xffff #define COMMAND_MASK 0xffff