sb/intel/i82801jx: Use common Intel SMM code
Use the common Intel code to set up smm and the smihandler. This is expected to break S3 resume and other smihandler related functionality as this code is meant to be used with CONFIG_SMM_TSEG. The platform (x4x) using this southbridge will adapt the CONFIG_SMM_TSEG codepath in subsequent patches. Change-Id: Id3b3b3abbb3920d68d77fd7db996a1dc3c6b85a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25596 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
parent
009518e79b
commit
6af3e6f4ff
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@ -28,6 +28,7 @@ config SOUTHBRIDGE_INTEL_I82801JX
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select SOUTHBRIDGE_INTEL_COMMON_GPIO
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select COMMON_FADT
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select SOUTHBRIDGE_INTEL_COMMON_SMM
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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if SOUTHBRIDGE_INTEL_I82801JX
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@ -24,6 +24,7 @@
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include <string.h>
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#include <southbridge/intel/common/pmutil.h>
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#include "i82801jx.h"
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/* I945/GM45 */
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@ -39,199 +40,6 @@
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*/
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static u16 pmbase = DEFAULT_PMBASE;
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/**
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* @brief read and clear PM1_STS
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* @return PM1_STS register
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*/
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static u16 reset_pm1_status(void)
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{
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u16 reg16;
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reg16 = inw(pmbase + PM1_STS);
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/* set status bits are cleared by writing 1 to them */
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outw(reg16, pmbase + PM1_STS);
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return reg16;
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}
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static void dump_pm1_status(u16 pm1_sts)
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{
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printk(BIOS_DEBUG, "PM1_STS: ");
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if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
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if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
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if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
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if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
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if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN ");
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if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL ");
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if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM ");
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if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF ");
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printk(BIOS_DEBUG, "\n");
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}
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/**
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* @brief read and clear SMI_STS
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* @return SMI_STS register
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*/
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static u32 reset_smi_status(void)
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{
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u32 reg32;
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reg32 = inl(pmbase + SMI_STS);
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/* set status bits are cleared by writing 1 to them */
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outl(reg32, pmbase + SMI_STS);
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return reg32;
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}
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static void dump_smi_status(u32 smi_sts)
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{
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printk(BIOS_DEBUG, "SMI_STS: ");
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if (smi_sts & (1 << 27)) printk(BIOS_DEBUG, "GPIO_UNLOCK ");
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if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
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if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
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if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
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if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
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if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
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if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
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if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
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if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
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if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
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if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
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if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
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if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
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if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
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if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
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if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
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if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
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if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
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if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
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if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
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printk(BIOS_DEBUG, "\n");
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}
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/**
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* @brief read and clear GPE0_STS
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* @return GPE0_STS register
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*/
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static u64 reset_gpe0_status(void)
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{
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u32 reg_h, reg_l;
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reg_l = inl(pmbase + GPE0_STS);
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reg_h = inl(pmbase + GPE0_STS + 4);
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/* set status bits are cleared by writing 1 to them */
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outl(reg_l, pmbase + GPE0_STS);
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outl(reg_h, pmbase + GPE0_STS + 4);
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return (((u64)reg_h) << 32) | reg_l;
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}
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static void dump_gpe0_status(u64 gpe0_sts)
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{
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int i;
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printk(BIOS_DEBUG, "GPE0_STS: ");
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if (gpe0_sts & (1LL << 32)) printk(BIOS_DEBUG, "USB6 ");
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for (i=31; i>= 16; i--) {
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if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
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}
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if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
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if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
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if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
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if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
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if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
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if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
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if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
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if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
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if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
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if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "USB5 ");
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if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
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if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
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if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE ");
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if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOT_PLUG ");
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if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
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printk(BIOS_DEBUG, "\n");
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}
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/**
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* @brief read and clear ALT_GP_SMI_STS
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* @return ALT_GP_SMI_STS register
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*/
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static u16 reset_alt_gp_smi_status(void)
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{
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u16 reg16;
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reg16 = inl(pmbase + ALT_GP_SMI_STS);
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/* set status bits are cleared by writing 1 to them */
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outl(reg16, pmbase + ALT_GP_SMI_STS);
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return reg16;
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}
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static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
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{
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int i;
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printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
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for (i=15; i>= 0; i--) {
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if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i);
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}
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printk(BIOS_DEBUG, "\n");
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}
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/**
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* @brief read and clear TCOx_STS
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* @return TCOx_STS registers
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*/
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static u32 reset_tco_status(void)
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{
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u32 tcobase = pmbase + 0x60;
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u32 reg32;
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reg32 = inl(tcobase + 0x04);
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/* set status bits are cleared by writing 1 to them */
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outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
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if (reg32 & (1 << 18))
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outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
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return reg32;
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}
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static void dump_tco_status(u32 tco_sts)
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{
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printk(BIOS_DEBUG, "TCO_STS: ");
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if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
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if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
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if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
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if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
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if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
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if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
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if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
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if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
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if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
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if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
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if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
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if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
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if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
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printk(BIOS_DEBUG, "\n");
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}
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/**
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* @brief Set the EOS bit
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*/
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static void smi_set_eos(void)
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{
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u8 reg8;
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reg8 = inb(pmbase + SMI_EN);
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reg8 |= EOS;
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outb(reg8, pmbase + SMI_EN);
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}
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extern uint8_t smm_relocation_start, smm_relocation_end;
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static void *default_smm_area = NULL;
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@ -371,14 +179,3 @@ void smm_lock(void)
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pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
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D_LCK | G_SMRAME | C_BASE_SEG);
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}
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void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
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{
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/* The GDT or coreboot table is going to live here. But a long time
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* after we relocated the GNVS, so this is not troublesome.
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*/
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*(u32 *)0x500 = (u32)gnvs;
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*(u32 *)0x504 = (u32)tcg;
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*(u32 *)0x508 = (u32)smi1;
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outb(APM_CNT_GNVS_UPDATE, 0xb2);
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}
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@ -22,6 +22,7 @@
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#include <cpu/x86/smm.h>
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#include <device/pci_def.h>
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#include <pc80/mc146818rtc.h>
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#include <southbridge/intel/common/pmutil.h>
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#include "i82801jx.h"
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#include "nvs.h"
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@ -39,160 +40,6 @@ global_nvs_t *gnvs = (global_nvs_t *)0x0;
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void *tcg = (void *)0x0;
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void *smi1 = (void *)0x0;
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/**
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* @brief read and clear PM1_STS
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* @return PM1_STS register
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*/
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static u16 reset_pm1_status(void)
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{
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u16 reg16;
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reg16 = inw(pmbase + PM1_STS);
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/* set status bits are cleared by writing 1 to them */
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outw(reg16, pmbase + PM1_STS);
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return reg16;
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}
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static void dump_pm1_status(u16 pm1_sts)
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{
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printk(BIOS_DEBUG, "PM1_STS: ");
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if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
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if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
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if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
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if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
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if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN ");
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if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL ");
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if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM ");
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if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF ");
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printk(BIOS_DEBUG, "\n");
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}
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/**
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* @brief read and clear SMI_STS
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* @return SMI_STS register
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*/
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static u32 reset_smi_status(void)
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{
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u32 reg32;
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reg32 = inl(pmbase + SMI_STS);
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/* set status bits are cleared by writing 1 to them */
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outl(reg32, pmbase + SMI_STS);
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return reg32;
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}
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static void dump_smi_status(u32 smi_sts)
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{
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printk(BIOS_DEBUG, "SMI_STS: ");
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if (smi_sts & (1 << 27)) printk(BIOS_DEBUG, "GPIO_UNLOCK ");
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if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
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if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
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if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
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if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
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if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
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if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
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if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
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if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
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if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
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if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
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if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
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if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
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if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
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if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
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if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
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if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
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if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
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if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
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if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
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printk(BIOS_DEBUG, "\n");
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}
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/**
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* @brief read and clear GPE0_STS
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* @return GPE0_STS register
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*/
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static u64 reset_gpe0_status(void)
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{
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u32 reg_h, reg_l;
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reg_l = inl(pmbase + GPE0_STS);
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reg_h = inl(pmbase + GPE0_STS + 4);
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/* set status bits are cleared by writing 1 to them */
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outl(reg_l, pmbase + GPE0_STS);
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outl(reg_h, pmbase + GPE0_STS + 4);
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return (((u64)reg_h) << 32) | reg_l;
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}
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static void dump_gpe0_status(u64 gpe0_sts)
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{
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int i;
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printk(BIOS_DEBUG, "GPE0_STS: ");
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if (gpe0_sts & (1LL << 32)) printk(BIOS_DEBUG, "USB6 ");
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for (i=31; i>= 16; i--) {
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if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
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}
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if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
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if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
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if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
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if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
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if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
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if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
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if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
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if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
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if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
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if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "USB5 ");
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if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
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if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
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if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE ");
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if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOT_PLUG ");
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if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
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printk(BIOS_DEBUG, "\n");
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}
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/**
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* @brief read and clear TCOx_STS
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* @return TCOx_STS registers
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*/
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static u32 reset_tco_status(void)
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{
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u32 tcobase = pmbase + 0x60;
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u32 reg32;
|
||||
|
||||
reg32 = inl(tcobase + 0x04);
|
||||
/* set status bits are cleared by writing 1 to them */
|
||||
outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
|
||||
if (reg32 & (1 << 18))
|
||||
outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
|
||||
|
||||
return reg32;
|
||||
}
|
||||
|
||||
|
||||
static void dump_tco_status(u32 tco_sts)
|
||||
{
|
||||
printk(BIOS_DEBUG, "TCO_STS: ");
|
||||
if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
|
||||
if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
|
||||
if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
|
||||
if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
|
||||
if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
|
||||
if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
|
||||
if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
|
||||
if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
|
||||
if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
|
||||
if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
|
||||
if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
|
||||
if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
|
||||
if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
int southbridge_io_trap_handler(int smif)
|
||||
{
|
||||
switch (smif) {
|
||||
|
|
@ -210,165 +57,15 @@ int southbridge_io_trap_handler(int smif)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the EOS bit
|
||||
*/
|
||||
void southbridge_smi_set_eos(void)
|
||||
void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)
|
||||
{
|
||||
u8 reg8;
|
||||
|
||||
reg8 = inb(pmbase + SMI_EN);
|
||||
reg8 |= EOS;
|
||||
outb(reg8, pmbase + SMI_EN);
|
||||
gnvs = *(global_nvs_t **)0x500;
|
||||
tcg = *(void **)0x504;
|
||||
smi1 = *(void **)0x508;
|
||||
*smm_done = 1;
|
||||
}
|
||||
|
||||
static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
|
||||
{
|
||||
u32 pmctrl;
|
||||
u8 reg8;
|
||||
|
||||
/* Emulate B2 register as the FADT / Linux expects it */
|
||||
|
||||
reg8 = inb(APM_CNT);
|
||||
if (mainboard_smi_apmc(reg8))
|
||||
return;
|
||||
|
||||
switch (reg8) {
|
||||
case APM_CNT_CST_CONTROL:
|
||||
/* Calling this function seems to cause
|
||||
* some kind of race condition in Linux
|
||||
* and causes a kernel oops
|
||||
*/
|
||||
printk(BIOS_DEBUG, "C-state control\n");
|
||||
break;
|
||||
case APM_CNT_PST_CONTROL:
|
||||
/* Calling this function seems to cause
|
||||
* some kind of race condition in Linux
|
||||
* and causes a kernel oops
|
||||
*/
|
||||
printk(BIOS_DEBUG, "P-state control\n");
|
||||
break;
|
||||
case APM_CNT_ACPI_DISABLE:
|
||||
pmctrl = inl(pmbase + PM1_CNT);
|
||||
pmctrl &= ~SCI_EN;
|
||||
outl(pmctrl, pmbase + PM1_CNT);
|
||||
printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
|
||||
break;
|
||||
case APM_CNT_ACPI_ENABLE:
|
||||
pmctrl = inl(pmbase + PM1_CNT);
|
||||
pmctrl |= SCI_EN;
|
||||
outl(pmctrl, pmbase + PM1_CNT);
|
||||
printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
|
||||
break;
|
||||
case APM_CNT_GNVS_UPDATE:
|
||||
if (smm_initialized) {
|
||||
printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
|
||||
return;
|
||||
}
|
||||
gnvs = *(global_nvs_t **)0x500;
|
||||
tcg = *(void **)0x504;
|
||||
smi1 = *(void **)0x508;
|
||||
smm_initialized = 1;
|
||||
printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8);
|
||||
}
|
||||
}
|
||||
|
||||
static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
|
||||
{
|
||||
u16 pm1_sts;
|
||||
volatile u8 cmos_status;
|
||||
|
||||
pm1_sts = reset_pm1_status();
|
||||
dump_pm1_status(pm1_sts);
|
||||
|
||||
/* While OSPM is not active, poweroff immediately
|
||||
* on a power button event.
|
||||
*/
|
||||
if (pm1_sts & PWRBTN_STS) {
|
||||
// power button pressed
|
||||
u32 reg32;
|
||||
reg32 = (7 << 10) | (1 << 13);
|
||||
outl(reg32, pmbase + PM1_CNT);
|
||||
}
|
||||
|
||||
if (pm1_sts & RTC_STS) {
|
||||
/* read RTC status register to disable the interrupt */
|
||||
cmos_status = cmos_read(RTC_REG_C);
|
||||
printk(BIOS_DEBUG, "RTC IRQ status: %02X\n", cmos_status);
|
||||
}
|
||||
}
|
||||
|
||||
static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
|
||||
{
|
||||
u32 gpe0_sts;
|
||||
|
||||
gpe0_sts = reset_gpe0_status();
|
||||
dump_gpe0_status(gpe0_sts);
|
||||
}
|
||||
|
||||
static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
|
||||
{
|
||||
u16 reg16;
|
||||
reg16 = inw(pmbase + ALT_GP_SMI_STS);
|
||||
outl(reg16, pmbase + ALT_GP_SMI_STS);
|
||||
|
||||
reg16 &= inw(pmbase + ALT_GP_SMI_EN);
|
||||
|
||||
mainboard_smi_gpi(reg16);
|
||||
|
||||
if (reg16)
|
||||
printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
|
||||
}
|
||||
|
||||
|
||||
static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)
|
||||
{
|
||||
u32 tco_sts;
|
||||
|
||||
tco_sts = reset_tco_status();
|
||||
|
||||
/* Any TCO event? */
|
||||
if (!tco_sts)
|
||||
return;
|
||||
|
||||
if (tco_sts & (1 << 8)) { // BIOSWR
|
||||
u8 bios_cntl;
|
||||
|
||||
bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
|
||||
|
||||
if (bios_cntl & 1) {
|
||||
/* BWE is RW, so the SMI was caused by a
|
||||
* write to BWE, not by a write to the BIOS
|
||||
*/
|
||||
|
||||
/* This is the place where we notice someone
|
||||
* is trying to tinker with the BIOS. We are
|
||||
* trying to be nice and just ignore it. A more
|
||||
* resolute answer would be to power down the
|
||||
* box.
|
||||
*/
|
||||
printk(BIOS_DEBUG, "Switching back to RO\n");
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
|
||||
} /* No else for now? */
|
||||
} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
|
||||
/* Handle TCO timeout */
|
||||
printk(BIOS_DEBUG, "TCO Timeout.\n");
|
||||
} else {
|
||||
dump_tco_status(tco_sts);
|
||||
}
|
||||
}
|
||||
|
||||
#if DEBUG_PERIODIC_SMIS
|
||||
static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Periodic SMI.\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
|
||||
void southbridge_smi_monitor(void)
|
||||
{
|
||||
#define IOTRAP(x) (trap_sts & (1 << x))
|
||||
u32 trap_sts, trap_cycle;
|
||||
|
|
@ -422,104 +119,6 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
|
|||
#undef IOTRAP
|
||||
}
|
||||
|
||||
typedef void (*smi_handler_t)(unsigned int node,
|
||||
smm_state_save_area_t *state_save);
|
||||
|
||||
smi_handler_t southbridge_smi[32] = {
|
||||
NULL, // [0] reserved
|
||||
NULL, // [1] reserved
|
||||
NULL, // [2] BIOS_STS
|
||||
NULL, // [3] LEGACY_USB_STS
|
||||
NULL, // [4] SLP_SMI_STS
|
||||
southbridge_smi_apmc, // [5] APM_STS
|
||||
NULL, // [6] SWSMI_TMR_STS
|
||||
NULL, // [7] reserved
|
||||
southbridge_smi_pm1, // [8] PM1_STS
|
||||
southbridge_smi_gpe0, // [9] GPE0_STS
|
||||
southbridge_smi_gpi, // [10] GPI_STS
|
||||
NULL, // [11] MCSMI_STS
|
||||
NULL, // [12] DEVMON_STS
|
||||
southbridge_smi_tco, // [13] TCO_STS
|
||||
#if DEBUG_PERIODIC_SMIS
|
||||
southbridge_smi_periodic, // [14] PERIODIC_STS
|
||||
#else
|
||||
NULL, // [14] PERIODIC_STS
|
||||
#endif
|
||||
NULL, // [15] SERIRQ_SMI_STS
|
||||
NULL, // [16] SMBUS_SMI_STS
|
||||
NULL, // [17] LEGACY_USB2_STS
|
||||
NULL, // [18] INTEL_USB2_STS
|
||||
NULL, // [19] reserved
|
||||
NULL, // [20] PCI_EXP_SMI_STS
|
||||
southbridge_smi_monitor, // [21] MONITOR_STS
|
||||
NULL, // [22] reserved
|
||||
NULL, // [23] reserved
|
||||
NULL, // [24] reserved
|
||||
NULL, // [25] reserved
|
||||
NULL, // [26] SPI_STS
|
||||
NULL, // [27] reserved
|
||||
NULL, // [28] reserved
|
||||
NULL, // [29] reserved
|
||||
NULL, // [30] reserved
|
||||
NULL // [31] reserved
|
||||
};
|
||||
|
||||
static u32 southbrigde_smi_mask_events(u32 smi_sts)
|
||||
void southbridge_finalize_all(void)
|
||||
{
|
||||
/* Clear all disabled bits in SMI_EN but the reserved ones. */
|
||||
smi_sts &= inl(pmbase + SMI_EN) | 0xf7f99700;
|
||||
|
||||
/* Check if SCI is enabled. */
|
||||
if (inl(pmbase + PM1_CNT) & SCI_EN)
|
||||
/* Clear PM1, GPE. */
|
||||
smi_sts &= ~((1 << 8) | (1 << 9));
|
||||
|
||||
/* Check if SPI generates SMI. */
|
||||
if (!(RCBA16(0x3806) & (1 << 15)) &&
|
||||
!(RCBA16(0x3891) & (1 << 15)))
|
||||
/* Clear SPI. */
|
||||
smi_sts &= ~(1 << 26);
|
||||
|
||||
return smi_sts;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Interrupt handler for SMI#
|
||||
*
|
||||
* @param node
|
||||
* @param *state_save
|
||||
*/
|
||||
void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
|
||||
{
|
||||
int i, dump = 0;
|
||||
u32 smi_sts;
|
||||
|
||||
/* Update global variable pmbase */
|
||||
pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), D31F0_PMBASE) & 0xfffc;
|
||||
|
||||
/* We need to clear the SMI status registers, or we won't see what's
|
||||
* happening in the following calls.
|
||||
*/
|
||||
smi_sts = reset_smi_status();
|
||||
|
||||
/* Filter all non-enabled SMI events */
|
||||
smi_sts = southbrigde_smi_mask_events(smi_sts);
|
||||
|
||||
/* Call SMI sub handler for each of the status bits */
|
||||
for (i = 0; i < 31; i++) {
|
||||
if (smi_sts & (1 << i)) {
|
||||
if (southbridge_smi[i])
|
||||
southbridge_smi[i](node, state_save);
|
||||
else {
|
||||
printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no "
|
||||
"handler available.\n", i);
|
||||
dump = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (dump) {
|
||||
dump_smi_status(smi_sts);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue