brya: add new skolas variant
Add a new skolas variant, which is a variant of brya's skolas baseboard. BUG=b:242869976 BRANCH=firmware-brya-14505.B TEST=none Change-Id: I7f9f0389d8b1bf75d8652cbcc9d0c15d3a529802 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Nick Vaccaro
parent
bbe0a99d66
commit
6afd7273e6
|
|
@ -153,6 +153,7 @@ config DRIVER_TPM_I2C_BUS
|
|||
default 0x1 if BOARD_GOOGLE_OSIRIS
|
||||
default 0x1 if BOARD_GOOGLE_MITHRAX
|
||||
default 0x1 if BOARD_GOOGLE_KULDAX
|
||||
default 0x1 if BOARD_GOOGLE_SKOLAS
|
||||
default 0x1 if BOARD_GOOGLE_SKOLAS4ES
|
||||
default 0x0 if BOARD_GOOGLE_JOXER
|
||||
default 0x0 if BOARD_GOOGLE_PUJJO
|
||||
|
|
@ -220,6 +221,7 @@ config MAINBOARD_PART_NUMBER
|
|||
default "Osiris" if BOARD_GOOGLE_OSIRIS
|
||||
default "Mithrax" if BOARD_GOOGLE_MITHRAX
|
||||
default "Kuldax" if BOARD_GOOGLE_KULDAX
|
||||
default "Skolas" if BOARD_GOOGLE_SKOLAS
|
||||
default "Skolas4ES" if BOARD_GOOGLE_SKOLAS4ES
|
||||
default "Joxer" if BOARD_GOOGLE_JOXER
|
||||
default "Pujjo" if BOARD_GOOGLE_PUJJO
|
||||
|
|
@ -258,6 +260,7 @@ config VARIANT_DIR
|
|||
default "osiris" if BOARD_GOOGLE_OSIRIS
|
||||
default "mithrax" if BOARD_GOOGLE_MITHRAX
|
||||
default "kuldax" if BOARD_GOOGLE_KULDAX
|
||||
default "skolas" if BOARD_GOOGLE_SKOLAS
|
||||
default "skolas4es" if BOARD_GOOGLE_SKOLAS4ES
|
||||
default "joxer" if BOARD_GOOGLE_JOXER
|
||||
default "pujjo" if BOARD_GOOGLE_PUJJO
|
||||
|
|
@ -298,7 +301,7 @@ config USE_PM_ACPI_TIMER
|
|||
|
||||
choice
|
||||
prompt "Cache as RAM (CAR) setup configuration to use"
|
||||
default USE_ADL_NEM if BOARD_GOOGLE_BRYA4ES || BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_NIVVIKS || BOARD_GOOGLE_NEREID || BOARD_GOOGLE_CRAASK || BOARD_GOOGLE_SKOLAS4ES || BOARD_GOOGLE_JOXER || BOARD_GOOGLE_PUJJO || BOARD_GOOGLE_XIVU || BOARD_GOOGLE_YAVIKS
|
||||
default USE_ADL_NEM if BOARD_GOOGLE_BRYA4ES || BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_NIVVIKS || BOARD_GOOGLE_NEREID || BOARD_GOOGLE_CRAASK || BOARD_GOOGLE_SKOLAS || BOARD_GOOGLE_SKOLAS4ES || BOARD_GOOGLE_JOXER || BOARD_GOOGLE_PUJJO || BOARD_GOOGLE_XIVU || BOARD_GOOGLE_YAVIKS
|
||||
default USE_ADL_ENEM
|
||||
|
||||
config USE_ADL_ENEM
|
||||
|
|
|
|||
|
|
@ -150,6 +150,13 @@ config BOARD_GOOGLE_REDRIX4ES
|
|||
select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
|
||||
select SOC_INTEL_COMMON_BLOCK_IPU
|
||||
|
||||
config BOARD_GOOGLE_SKOLAS
|
||||
bool "-> Skolas"
|
||||
select BOARD_GOOGLE_BASEBOARD_SKOLAS
|
||||
select DRIVERS_GENESYSLOGIC_GL9755
|
||||
select DRIVERS_INTEL_MIPI_CAMERA
|
||||
select SOC_INTEL_COMMON_BLOCK_IPU
|
||||
|
||||
config BOARD_GOOGLE_SKOLAS4ES
|
||||
bool "-> Skolas4ES"
|
||||
select BOARD_GOOGLE_BASEBOARD_SKOLAS
|
||||
|
|
|
|||
|
|
@ -0,0 +1,6 @@
|
|||
bootblock-y += gpio.c
|
||||
romstage-y += gpio.c
|
||||
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
|
||||
ramstage-$(CONFIG_FW_CONFIG) += variant.c
|
||||
ramstage-y += gpio.c
|
||||
ramstage-y += ramstage.c
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <bootstate.h>
|
||||
#include <console/console.h>
|
||||
#include <fw_config.h>
|
||||
#include <gpio.h>
|
||||
|
||||
static const struct pad_config dmic_enable_pads[] = {
|
||||
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC_CLK0_R */
|
||||
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC_DATA0_R */
|
||||
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC_CLK1_R */
|
||||
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC_DATA1_R */
|
||||
};
|
||||
|
||||
static const struct pad_config dmic_disable_pads[] = {
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
};
|
||||
|
||||
static const struct pad_config sndw_enable_pads[] = {
|
||||
PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), /* SDW_HP_CLK_R */
|
||||
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SDW_HP_DATA_R */
|
||||
PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), /* SDW_SPKR_CLK */
|
||||
PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), /* SDW_SPKR_DATA */
|
||||
};
|
||||
|
||||
static const struct pad_config max98360_enable_pads[] = {
|
||||
PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */
|
||||
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */
|
||||
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */
|
||||
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */
|
||||
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC_CLK0_R */
|
||||
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC_DATA0_R */
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK1_R */
|
||||
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA1_R */
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
};
|
||||
|
||||
static const struct pad_config sndw_disable_pads[] = {
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
};
|
||||
|
||||
static const struct pad_config i2s0_enable_pads[] = {
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */
|
||||
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */
|
||||
PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */
|
||||
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */
|
||||
};
|
||||
|
||||
static const struct pad_config i2s2_enable_pads[] = {
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */
|
||||
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */
|
||||
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S_PCH_TX_SPKR_RX_R */
|
||||
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S_PCH_RX_SPKR_TX */
|
||||
};
|
||||
|
||||
static const struct pad_config i2s0_disable_pads[] = {
|
||||
PAD_NC(GPP_R0, NONE),
|
||||
PAD_NC(GPP_R1, NONE),
|
||||
PAD_NC(GPP_R2, NONE),
|
||||
PAD_NC(GPP_R3, NONE),
|
||||
};
|
||||
|
||||
static const struct pad_config i2s2_disable_pads[] = {
|
||||
PAD_NC(GPP_R4, NONE),
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
};
|
||||
|
||||
static const struct pad_config bt_i2s_enable_pads[] = {
|
||||
PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */
|
||||
PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */
|
||||
PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */
|
||||
PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */
|
||||
PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */
|
||||
PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */
|
||||
PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */
|
||||
PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */
|
||||
};
|
||||
|
||||
static const struct pad_config bt_i2s_disable_pads[] = {
|
||||
PAD_NC(GPP_VGPIO_30, NONE),
|
||||
PAD_NC(GPP_VGPIO_31, NONE),
|
||||
PAD_NC(GPP_VGPIO_32, NONE),
|
||||
PAD_NC(GPP_VGPIO_33, NONE),
|
||||
PAD_NC(GPP_VGPIO_34, NONE),
|
||||
PAD_NC(GPP_VGPIO_35, NONE),
|
||||
PAD_NC(GPP_VGPIO_36, NONE),
|
||||
PAD_NC(GPP_VGPIO_37, NONE),
|
||||
};
|
||||
|
||||
static void enable_i2s(void)
|
||||
{
|
||||
gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
|
||||
gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads));
|
||||
gpio_configure_pads(i2s2_enable_pads, ARRAY_SIZE(i2s2_enable_pads));
|
||||
gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads));
|
||||
}
|
||||
|
||||
static void fw_config_handle(void *unused)
|
||||
{
|
||||
if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
|
||||
printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
|
||||
gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads));
|
||||
gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
|
||||
gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
|
||||
gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads));
|
||||
return;
|
||||
}
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW))) {
|
||||
printk(BIOS_INFO, "Configure audio over SoundWire with MAX98373 ALC5682.\n");
|
||||
gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
|
||||
gpio_configure_pads(sndw_enable_pads, ARRAY_SIZE(sndw_enable_pads));
|
||||
printk(BIOS_INFO, "BT offload enabled\n");
|
||||
gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads));
|
||||
gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
|
||||
gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
|
||||
} else if (!fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) {
|
||||
printk(BIOS_INFO, "BT offload disabled\n");
|
||||
gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads));
|
||||
gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
|
||||
gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
|
||||
}
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S))) {
|
||||
printk(BIOS_INFO, "Configure audio over I2S with MAX98357 ALC5682I.\n");
|
||||
enable_i2s();
|
||||
}
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(AUDIO, ALC1019_NAU88L25B_I2S))) {
|
||||
printk(BIOS_INFO, "Configure audio over I2S with ALC1019 NAU88L25B.\n");
|
||||
enable_i2s();
|
||||
}
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) {
|
||||
printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I.\n");
|
||||
gpio_configure_pads(max98360_enable_pads, ARRAY_SIZE(max98360_enable_pads));
|
||||
printk(BIOS_INFO, "BT offload enabled\n");
|
||||
gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads));
|
||||
gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
|
||||
}
|
||||
}
|
||||
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
|
||||
|
|
@ -0,0 +1,204 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <boardid.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config board_id0_1_overrides[] = {
|
||||
/* B2 : VRALERT# ==> NC */
|
||||
PAD_NC(GPP_B2, NONE),
|
||||
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
|
||||
PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
|
||||
/* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
|
||||
PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
|
||||
/* B15 : TIME_SYNC0 ==> NC */
|
||||
PAD_NC(GPP_B15, NONE),
|
||||
/* C3 : SML0CLK ==> NC */
|
||||
PAD_NC(GPP_C3, NONE),
|
||||
/* C4 : SML0DATA ==> NC */
|
||||
PAD_NC(GPP_C4, NONE),
|
||||
/* D13 : ISH_UART0_RXD ==> PCH_I2C_CAM_SDA */
|
||||
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3),
|
||||
/* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */
|
||||
PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3),
|
||||
/* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */
|
||||
PAD_CFG_GPI(GPP_F19, UP_20K, DEEP),
|
||||
/* F20 : EXT_PWR_GATE# ==> HPS_RST_R */
|
||||
PAD_CFG_GPO(GPP_F20, 0, DEEP),
|
||||
/* F21 : EXT_PWR_GATE2# ==> WAKE_ON_WWAN_ODL */
|
||||
PAD_NC(GPP_F21, NONE),
|
||||
/* H21 : IMGCLKOUT2 ==> WLAN_INT_L */
|
||||
PAD_CFG_GPI_APIC(GPP_H21, NONE, DEEP, EDGE_SINGLE, NONE),
|
||||
/* GPD2: LAN_WAKE# ==> NC */
|
||||
PAD_NC(GPD2, NONE),
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock for board id < 2 */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
|
||||
/* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
|
||||
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
|
||||
/*
|
||||
* D1 : ISH_GP1 ==> FP_RST_ODL
|
||||
* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
|
||||
* To ensure proper power sequencing for the FPMCU device, reset signal is driven low
|
||||
* early on in bootblock, followed by enabling of power. Reset signal is deasserted
|
||||
* later on in ramstage. Since reset signal is asserted in bootblock, it results in
|
||||
* FPMCU not working after a S3 resume. This is a known issue.
|
||||
*/
|
||||
PAD_CFG_GPO(GPP_D1, 0, DEEP),
|
||||
/* D2 : ISH_GP2 ==> EN_FP_PWR */
|
||||
PAD_CFG_GPO(GPP_D2, 1, DEEP),
|
||||
/* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
|
||||
PAD_CFG_GPO(GPP_E0, 0, DEEP),
|
||||
/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
|
||||
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
|
||||
/* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
|
||||
PAD_CFG_GPO(GPP_E16, 0, DEEP),
|
||||
/* E15 : RSVD_TP ==> PCH_WP_OD */
|
||||
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
|
||||
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
/* F21 : EXT_PWR_GATE2# ==> NC */
|
||||
PAD_NC(GPP_F21, NONE),
|
||||
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
/* H13 : I2C7_SCL ==> EN_PP3300_SD */
|
||||
PAD_NC(GPP_H13, UP_20K),
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock for board id 2 */
|
||||
static const struct pad_config early_gpio_table_id2[] = {
|
||||
/* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
|
||||
PAD_CFG_GPO(GPP_A12, 1, DEEP),
|
||||
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* B4 : PROC_GP3 ==> SSD_PERST_L */
|
||||
PAD_CFG_GPO(GPP_B4, 0, DEEP),
|
||||
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
|
||||
/* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
|
||||
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
|
||||
/*
|
||||
* D1 : ISH_GP1 ==> FP_RST_ODL
|
||||
* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
|
||||
* To ensure proper power sequencing for the FPMCU device, reset signal is driven low
|
||||
* early on in bootblock, followed by enabling of power. Reset signal is deasserted
|
||||
* later on in ramstage. Since reset signal is asserted in bootblock, it results in
|
||||
* FPMCU not working after a S3 resume. This is a known issue.
|
||||
*/
|
||||
PAD_CFG_GPO(GPP_D1, 0, DEEP),
|
||||
/* D2 : ISH_GP2 ==> EN_FP_PWR */
|
||||
PAD_CFG_GPO(GPP_D2, 1, DEEP),
|
||||
/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
|
||||
PAD_CFG_GPO(GPP_D11, 1, DEEP),
|
||||
/* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
|
||||
PAD_CFG_GPO(GPP_E0, 0, DEEP),
|
||||
/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
|
||||
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
|
||||
/* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
|
||||
PAD_CFG_GPO(GPP_E16, 0, DEEP),
|
||||
/* E15 : RSVD_TP ==> PCH_WP_OD */
|
||||
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
|
||||
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
|
||||
PAD_CFG_GPO(GPP_F21, 0, DEEP),
|
||||
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
/* H13 : I2C7_SCL ==> EN_PP3300_SD */
|
||||
PAD_NC(GPP_H13, UP_20K),
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock for board id 4 */
|
||||
static const struct pad_config early_gpio_table_id4[] = {
|
||||
/* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
|
||||
PAD_CFG_GPO(GPP_A12, 1, DEEP),
|
||||
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* B4 : PROC_GP3 ==> SSD_PERST_L */
|
||||
PAD_CFG_GPO(GPP_B4, 0, DEEP),
|
||||
/* H6 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
/* H7 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
/*
|
||||
* D1 : ISH_GP1 ==> FP_RST_ODL
|
||||
* FP_RST_ODL comes out of reset as hi-z and does not have an external
|
||||
* pull-down. To ensure proper power sequencing for the FPMCU device,
|
||||
* reset signal is driven low early on in bootblock, followed by
|
||||
* enabling of power. Reset signal is deasserted later on in ramstage.
|
||||
* Since reset signal is asserted in bootblock, it results in FPMCU not
|
||||
* working after a S3 resume. This is a known issue.
|
||||
*/
|
||||
PAD_CFG_GPO(GPP_D1, 0, DEEP),
|
||||
/* D2 : ISH_GP2 ==> EN_FP_PWR */
|
||||
PAD_CFG_GPO(GPP_D2, 1, DEEP),
|
||||
/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
|
||||
PAD_CFG_GPO(GPP_D11, 1, DEEP),
|
||||
/* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
|
||||
PAD_CFG_GPO(GPP_E0, 0, DEEP),
|
||||
/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
|
||||
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
|
||||
/* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
|
||||
PAD_CFG_GPO(GPP_E16, 0, DEEP),
|
||||
/* E15 : RSVD_TP ==> PCH_WP_OD */
|
||||
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
|
||||
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
|
||||
PAD_CFG_GPO(GPP_F21, 0, DEEP),
|
||||
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
/* H13 : I2C7_SCL ==> EN_PP3300_SD */
|
||||
PAD_NC(GPP_H13, UP_20K),
|
||||
};
|
||||
|
||||
static const struct pad_config romstage_gpio_table[] = {
|
||||
/* B4 : PROC_GP3 ==> SSD_PERST_L */
|
||||
PAD_CFG_GPO(GPP_B4, 1, DEEP),
|
||||
/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
|
||||
PAD_CFG_GPO(GPP_F21, 1, DEEP),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_override_table(size_t *num)
|
||||
{
|
||||
const uint32_t id = board_id();
|
||||
if (id == BOARD_ID_UNKNOWN || id < 2) {
|
||||
*num = ARRAY_SIZE(board_id0_1_overrides);
|
||||
return board_id0_1_overrides;
|
||||
}
|
||||
|
||||
*num = 0;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
const uint32_t id = board_id();
|
||||
if (id == BOARD_ID_UNKNOWN || id < 2) {
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
} else if (id >= 4) {
|
||||
*num = ARRAY_SIZE(early_gpio_table_id4);
|
||||
return early_gpio_table_id4;
|
||||
}
|
||||
|
||||
*num = ARRAY_SIZE(early_gpio_table_id2);
|
||||
return early_gpio_table_id2;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_romstage_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(romstage_gpio_table);
|
||||
return romstage_gpio_table;
|
||||
}
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef MAINBOARD_EC_H
|
||||
#define MAINBOARD_EC_H
|
||||
|
||||
#include <baseboard/ec.h>
|
||||
|
||||
#endif /* MAINBOARD_GPIO_H */
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __MAINBOARD_GPIO_H__
|
||||
#define __MAINBOARD_GPIO_H__
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#define WWAN_FCPO GPP_F21
|
||||
#define WWAN_RST GPP_E16
|
||||
#define WWAN_PERST GPP_E0
|
||||
#define T1_OFF_MS 16
|
||||
#define T2_OFF_MS 2
|
||||
|
||||
#endif /* __MAINBOARD_GPIO_H__ */
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/skolas/memory src/mainboard/google/brya/variants/skolas/memory/mem_parts_used.txt
|
||||
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D1NP-046 WT:B
|
||||
SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A
|
||||
SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 2(0b0010) Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C
|
||||
SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 3(0b0011) Parts = H9HCNNNCPMMLXR-NEE, MT53E1G32D2NP-046 WT:B
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/skolas/memory src/mainboard/google/brya/variants/skolas/memory/mem_parts_used.txt
|
||||
|
||||
DRAM Part Name ID to assign
|
||||
MT53E512M32D2NP-046 WT:F 0 (0000)
|
||||
H9HCNNNBKMMLXR-NEE 0 (0000)
|
||||
MT53E1G32D2NP-046 WT:A 1 (0001)
|
||||
MT53E2G32D4NQ-046 WT:A 2 (0010)
|
||||
H9HCNNNCPMMLXR-NEE 3 (0011)
|
||||
MT53E1G32D2NP-046 WT:B 3 (0011)
|
||||
MT53E2G32D4NQ-046 WT:C 2 (0010)
|
||||
MT53E512M32D1NP-046 WT:B 0 (0000)
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
MT53E512M32D2NP-046 WT:F
|
||||
H9HCNNNBKMMLXR-NEE
|
||||
MT53E1G32D2NP-046 WT:A
|
||||
MT53E2G32D4NQ-046 WT:A
|
||||
H9HCNNNCPMMLXR-NEE
|
||||
MT53E1G32D2NP-046 WT:B
|
||||
MT53E2G32D4NQ-046 WT:C
|
||||
MT53E512M32D1NP-046 WT:B
|
||||
|
|
@ -0,0 +1,831 @@
|
|||
fw_config
|
||||
field DB_USB 0 3
|
||||
option USB_ABSENT 0
|
||||
option USB3_PS8815 1
|
||||
end
|
||||
field DB_SD 4 5
|
||||
option SD_ABSENT 0
|
||||
option SD_GL9755S 1
|
||||
end
|
||||
field KB_BL 7 7
|
||||
option KB_BL_ABSENT 0
|
||||
option KB_BL_PRESENT 1
|
||||
end
|
||||
field AUDIO 8 10
|
||||
option AUDIO_UNKNOWN 0
|
||||
option MAX98357_ALC5682I_I2S 1
|
||||
option MAX98373_ALC5682_SNDW 2
|
||||
option MAX98373_NAU88L25B_I2S 3
|
||||
option ALC1019_NAU88L25B_I2S 4
|
||||
option MAX98360_ALC5682I_I2S 5
|
||||
end
|
||||
field DB_LTE 11 12
|
||||
option LTE_ABSENT 0
|
||||
option LTE_USB 1
|
||||
option LTE_PCIE 2
|
||||
end
|
||||
field UFC 13 14
|
||||
option UFC_USB 0
|
||||
option UFC_MIPI_IMX208 1
|
||||
end
|
||||
field WFC 15 16
|
||||
option WFC_ABSENT 0
|
||||
option WFC_MIPI_OVTI5675 1
|
||||
option WFC_MIPI_OVTI8856 2
|
||||
end
|
||||
field HPS 17 17
|
||||
option HPS_ABSENT 0
|
||||
option HPS_PRESENT 1
|
||||
end
|
||||
end
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "sagv" = "SaGv_Enabled"
|
||||
|
||||
register "platform_pmax" = "145"
|
||||
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
|
||||
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
|
||||
|
||||
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
|
||||
|
||||
# FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn
|
||||
# bypass rails implemented.
|
||||
register "ext_fivr_settings" = "{
|
||||
.configure_ext_fivr = 1,
|
||||
}"
|
||||
|
||||
# Intel Common SoC Config
|
||||
#+-------------------+---------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------------+---------------------------+
|
||||
#| GSPI1 | Fingerprint MCU |
|
||||
#| I2C0 | Audio |
|
||||
#| I2C1 | cr50 TPM. Early init is |
|
||||
#| | required to set up a BAR |
|
||||
#| | for TPM communication |
|
||||
#| I2C2 | SAR |
|
||||
#| I2C3 | TouchScreen |
|
||||
#| I2C5 | Trackpad |
|
||||
#+-------------------+---------------------------+
|
||||
register "common_soc_config" = "{
|
||||
.i2c[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 650,
|
||||
.fall_time_ns = 400,
|
||||
.data_hold_time_ns = 50,
|
||||
},
|
||||
.i2c[1] = {
|
||||
.early_init = 1,
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 600,
|
||||
.fall_time_ns = 400,
|
||||
.data_hold_time_ns = 50,
|
||||
},
|
||||
.i2c[2] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 900,
|
||||
.fall_time_ns = 400,
|
||||
.data_hold_time_ns = 50,
|
||||
},
|
||||
.i2c[3] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 650,
|
||||
.fall_time_ns = 400,
|
||||
.data_hold_time_ns = 50,
|
||||
},
|
||||
.i2c[5] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 650,
|
||||
.fall_time_ns = 400,
|
||||
.data_hold_time_ns = 50,
|
||||
},
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device ref dtt on
|
||||
chip drivers/intel/dptf
|
||||
## sensor information
|
||||
register "options.tsr[0].desc" = ""DRAM_SOC""
|
||||
register "options.tsr[1].desc" = ""Ambient""
|
||||
register "options.tsr[2].desc" = ""Charger""
|
||||
register "options.tsr[3].desc" = ""WWAN""
|
||||
|
||||
# TODO: below values are initial reference values only
|
||||
## Active Policy
|
||||
register "policies.active" = "{
|
||||
[0] = {
|
||||
.target = DPTF_CPU,
|
||||
.thresholds = {
|
||||
TEMP_PCT(85, 90),
|
||||
TEMP_PCT(80, 80),
|
||||
TEMP_PCT(75, 70),
|
||||
TEMP_PCT(70, 50),
|
||||
TEMP_PCT(65, 30),
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.target = DPTF_TEMP_SENSOR_1,
|
||||
.thresholds = {
|
||||
TEMP_PCT(50, 90),
|
||||
TEMP_PCT(48, 70),
|
||||
TEMP_PCT(46, 60),
|
||||
TEMP_PCT(43, 40),
|
||||
TEMP_PCT(40, 30),
|
||||
}
|
||||
}
|
||||
}"
|
||||
|
||||
## Passive Policy
|
||||
register "policies.passive" = "{
|
||||
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
|
||||
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
|
||||
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000),
|
||||
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
|
||||
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000),
|
||||
}"
|
||||
|
||||
## Critical Policy
|
||||
register "policies.critical" = "{
|
||||
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
|
||||
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
|
||||
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
|
||||
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
|
||||
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
|
||||
}"
|
||||
|
||||
register "controls.power_limits" = "{
|
||||
.pl1 = {
|
||||
.min_power = 3000,
|
||||
.max_power = 15000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 200,
|
||||
},
|
||||
.pl2 = {
|
||||
.min_power = 55000,
|
||||
.max_power = 55000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 1000,
|
||||
}
|
||||
}"
|
||||
|
||||
## Charger Performance Control (Control, mA)
|
||||
register "controls.charger_perf" = "{
|
||||
[0] = { 255, 1700 },
|
||||
[1] = { 24, 1500 },
|
||||
[2] = { 16, 1000 },
|
||||
[3] = { 8, 500 }
|
||||
}"
|
||||
|
||||
## Fan Performance Control (Percent, Speed, Noise, Power)
|
||||
register "controls.fan_perf" = "{
|
||||
[0] = { 90, 6700, 220, 2200, },
|
||||
[1] = { 80, 5800, 180, 1800, },
|
||||
[2] = { 70, 5000, 145, 1450, },
|
||||
[3] = { 60, 4900, 115, 1150, },
|
||||
[4] = { 50, 3838, 90, 900, },
|
||||
[5] = { 40, 2904, 55, 550, },
|
||||
[6] = { 30, 2337, 30, 300, },
|
||||
[7] = { 20, 1608, 15, 150, },
|
||||
[8] = { 10, 800, 10, 100, },
|
||||
[9] = { 0, 0, 0, 50, }
|
||||
}"
|
||||
|
||||
## Fan options
|
||||
register "options.fan.fine_grained_control" = "1"
|
||||
register "options.fan.step_size" = "2"
|
||||
|
||||
device generic 0 alias dptf_policy on end
|
||||
end
|
||||
end
|
||||
device ref ipu on
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "0x50000"
|
||||
register "acpi_name" = ""IPU0""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
|
||||
|
||||
register "cio2_num_ports" = "1"
|
||||
register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used
|
||||
register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0""
|
||||
register "cio2_prt[0]" = "2"
|
||||
device generic 0 on
|
||||
# MIPI lanes are split between UFC and WFC depending on
|
||||
# whether the UFC is USB or MIPI hence probing UFC_USB
|
||||
probe UFC UFC_USB
|
||||
end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "0x50000"
|
||||
register "acpi_name" = ""IPU0""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
|
||||
|
||||
register "cio2_num_ports" = "2"
|
||||
register "cio2_lanes_used" = "{4,2}" # 4 and 2 CSI Camera lanes are used
|
||||
register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0""
|
||||
register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1""
|
||||
register "cio2_prt[0]" = "2"
|
||||
register "cio2_prt[1]" = "1"
|
||||
device generic 1 on
|
||||
probe UFC UFC_MIPI_IMX208
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref cnvi_wifi on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
register "enable_cnvi_ddr_rfim" = "true"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp6 on
|
||||
# Enable WWAN PCIE 6 using clk 5
|
||||
register "pch_pcie_rp[PCH_RP(6)]" = "{
|
||||
.clk_src = 5,
|
||||
.clk_req = 5,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
|
||||
register "reset_off_delay_ms" = "20"
|
||||
# register "reset_delay_ms" = "1000"
|
||||
register "srcclk_pin" = "5"
|
||||
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
|
||||
register "skip_on_off_support" = "true"
|
||||
device generic 0 alias rp6_rtd3 on
|
||||
probe DB_LTE LTE_PCIE
|
||||
end
|
||||
end
|
||||
chip drivers/wwan/fm
|
||||
register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
|
||||
register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
|
||||
register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
use rp6_rtd3 as rtd3dev
|
||||
device generic 0 on
|
||||
probe DB_LTE LTE_PCIE
|
||||
end
|
||||
end
|
||||
probe DB_LTE LTE_PCIE
|
||||
end
|
||||
device ref tcss_dma0 on
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
|
||||
use tcss_usb3_port1 as dfp[0].typec_port
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref tcss_dma1 on
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
|
||||
use tcss_usb3_port3 as dfp[0].typec_port
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp8 on
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
|
||||
register "srcclk_pin" = "3"
|
||||
device generic 0 on end
|
||||
end
|
||||
end #PCIE8 SD card
|
||||
device ref i2c0 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""10EC5682""
|
||||
register "name" = ""RT58""
|
||||
register "desc" = ""Headset Codec""
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
|
||||
# Set the jd_src to RT5668_JD1 for jack detection
|
||||
register "property_count" = "1"
|
||||
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||
register "property_list[0].name" = ""realtek,jd-src""
|
||||
register "property_list[0].integer" = "1"
|
||||
device i2c 1a on
|
||||
probe AUDIO MAX98357_ALC5682I_I2S
|
||||
probe AUDIO MAX98360_ALC5682I_I2S
|
||||
end
|
||||
end
|
||||
chip drivers/i2c/nau8825
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
|
||||
register "jkdet_enable" = "1"
|
||||
register "jkdet_pull_enable" = "0"
|
||||
register "jkdet_polarity" = "1" # ActiveLow
|
||||
register "vref_impedance" = "2" # 125kOhm
|
||||
register "micbias_voltage" = "6" # 2.754
|
||||
register "sar_threshold_num" = "4"
|
||||
register "sar_threshold[0]" = "0x0c"
|
||||
register "sar_threshold[1]" = "0x1c"
|
||||
register "sar_threshold[2]" = "0x38"
|
||||
register "sar_threshold[3]" = "0x60"
|
||||
register "sar_hysteresis" = "1"
|
||||
register "sar_voltage" = "0" # VDDA
|
||||
register "sar_compare_time" = "0" # 500ns
|
||||
register "sar_sampling_time" = "0" # 2us
|
||||
register "short_key_debounce" = "2" # 100ms
|
||||
register "jack_insert_debounce" = "7" # 512ms
|
||||
register "jack_eject_debounce" = "7" # 512ms
|
||||
device i2c 1a on
|
||||
probe AUDIO ALC1019_NAU88L25B_I2S
|
||||
end
|
||||
end
|
||||
chip drivers/generic/alc1015
|
||||
register "hid" = ""RTL1019""
|
||||
register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
|
||||
device generic 1 on
|
||||
probe AUDIO ALC1019_NAU88L25B_I2S
|
||||
end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_hid" = ""OVTI8856""
|
||||
register "acpi_uid" = "0"
|
||||
register "acpi_name" = ""CAM0""
|
||||
register "chip_name" = ""Ov 8856 Camera""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
|
||||
|
||||
register "ssdb.lanes_used" = "4"
|
||||
register "ssdb.link_used" = "0"
|
||||
register "ssdb.vcm_type" = "0x0C"
|
||||
register "vcm_name" = ""VCM0""
|
||||
register "num_freq_entries" = "2"
|
||||
register "link_freq[0]" = "360 * MHz" # 360 MHz
|
||||
register "link_freq[1]" = "180 * MHz" # 180 MHz
|
||||
register "remote_name" = ""IPU0""
|
||||
|
||||
register "has_power_resource" = "1"
|
||||
#Controls
|
||||
register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
|
||||
register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
|
||||
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #power_enable_2p8
|
||||
register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #power_enable_1p2
|
||||
register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset
|
||||
|
||||
#_ON
|
||||
register "on_seq.ops_cnt" = "5"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
|
||||
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
|
||||
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
|
||||
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
|
||||
register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
|
||||
|
||||
#_OFF
|
||||
register "off_seq.ops_cnt" = "4"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
|
||||
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
|
||||
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
|
||||
register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 10 on end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "2"
|
||||
register "acpi_name" = ""VCM0""
|
||||
register "chip_name" = ""DW9768 VCM""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_VCM"
|
||||
|
||||
register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC""
|
||||
register "vcm_compat" = ""dongwoon,dw9768""
|
||||
|
||||
device i2c 0C on end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "1"
|
||||
register "acpi_name" = ""NVM0""
|
||||
register "chip_name" = ""AT24 EEPROM""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_NVM"
|
||||
|
||||
register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC""
|
||||
register "nvm_compat" = ""atmel,24c1024""
|
||||
|
||||
register "nvm_size" = "0x2800"
|
||||
register "nvm_pagesize" = "0x01"
|
||||
register "nvm_readonly" = "0x01"
|
||||
register "nvm_width" = "0x10"
|
||||
|
||||
device i2c 58 on end
|
||||
end
|
||||
end #I2C0
|
||||
device ref i2c1 on
|
||||
chip drivers/i2c/tpm
|
||||
register "hid" = ""GOOG0005""
|
||||
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
|
||||
device i2c 50 on end
|
||||
end
|
||||
end #I2C1
|
||||
device ref i2c2 on
|
||||
chip drivers/i2c/sx9324
|
||||
register "desc" = ""SAR1 Proximity Sensor""
|
||||
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
|
||||
register "speed" = "I2C_SPEED_FAST"
|
||||
register "uid" = "1"
|
||||
register "reg_gnrl_ctrl0" = "0x16"
|
||||
register "reg_gnrl_ctrl1" = "0x21"
|
||||
register "reg_afe_ctrl0" = "0x00"
|
||||
register "reg_afe_ctrl1" = "0x10"
|
||||
register "reg_afe_ctrl2" = "0x00"
|
||||
register "reg_afe_ctrl3" = "0x00"
|
||||
register "reg_afe_ctrl4" = "0x07"
|
||||
register "reg_afe_ctrl5" = "0x00"
|
||||
register "reg_afe_ctrl6" = "0x00"
|
||||
register "reg_afe_ctrl7" = "0x07"
|
||||
register "reg_afe_ctrl8" = "0x12"
|
||||
register "reg_afe_ctrl9" = "0x0f"
|
||||
register "reg_prox_ctrl0" = "0x12"
|
||||
register "reg_prox_ctrl1" = "0x12"
|
||||
register "reg_prox_ctrl2" = "0x90"
|
||||
register "reg_prox_ctrl3" = "0x60"
|
||||
register "reg_prox_ctrl4" = "0x0c"
|
||||
register "reg_prox_ctrl5" = "0x12"
|
||||
register "reg_prox_ctrl6" = "0x3c"
|
||||
register "reg_prox_ctrl7" = "0x58"
|
||||
register "reg_adv_ctrl0" = "0x00"
|
||||
register "reg_adv_ctrl1" = "0x00"
|
||||
register "reg_adv_ctrl2" = "0x00"
|
||||
register "reg_adv_ctrl3" = "0x00"
|
||||
register "reg_adv_ctrl4" = "0x00"
|
||||
register "reg_adv_ctrl5" = "0x05"
|
||||
register "reg_adv_ctrl6" = "0x00"
|
||||
register "reg_adv_ctrl7" = "0x00"
|
||||
register "reg_adv_ctrl8" = "0x00"
|
||||
register "reg_adv_ctrl9" = "0x00"
|
||||
register "reg_adv_ctrl10" = "0x5c"
|
||||
register "reg_adv_ctrl11" = "0x52"
|
||||
register "reg_adv_ctrl12" = "0xb5"
|
||||
register "reg_adv_ctrl13" = "0x00"
|
||||
register "reg_adv_ctrl14" = "0x80"
|
||||
register "reg_adv_ctrl15" = "0x0c"
|
||||
register "reg_adv_ctrl16" = "0x38"
|
||||
register "reg_adv_ctrl17" = "0x56"
|
||||
register "reg_adv_ctrl18" = "0x33"
|
||||
register "reg_adv_ctrl19" = "0xf0"
|
||||
register "reg_adv_ctrl20" = "0xf0"
|
||||
device i2c 28 on end
|
||||
end
|
||||
chip drivers/i2c/sx9324
|
||||
register "desc" = ""SAR2 Proximity Sensor""
|
||||
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
|
||||
register "speed" = "I2C_SPEED_FAST"
|
||||
register "uid" = "2"
|
||||
register "reg_gnrl_ctrl0" = "0x16"
|
||||
register "reg_gnrl_ctrl1" = "0x21"
|
||||
register "reg_afe_ctrl0" = "0x00"
|
||||
register "reg_afe_ctrl1" = "0x10"
|
||||
register "reg_afe_ctrl2" = "0x00"
|
||||
register "reg_afe_ctrl3" = "0x00"
|
||||
register "reg_afe_ctrl4" = "0x07"
|
||||
register "reg_afe_ctrl5" = "0x00"
|
||||
register "reg_afe_ctrl6" = "0x00"
|
||||
register "reg_afe_ctrl7" = "0x07"
|
||||
register "reg_afe_ctrl8" = "0x12"
|
||||
register "reg_afe_ctrl9" = "0x0f"
|
||||
register "reg_prox_ctrl0" = "0x12"
|
||||
register "reg_prox_ctrl1" = "0x12"
|
||||
register "reg_prox_ctrl2" = "0x90"
|
||||
register "reg_prox_ctrl3" = "0x60"
|
||||
register "reg_prox_ctrl4" = "0x0c"
|
||||
register "reg_prox_ctrl5" = "0x12"
|
||||
register "reg_prox_ctrl6" = "0x3c"
|
||||
register "reg_prox_ctrl7" = "0x58"
|
||||
register "reg_adv_ctrl0" = "0x00"
|
||||
register "reg_adv_ctrl1" = "0x00"
|
||||
register "reg_adv_ctrl2" = "0x00"
|
||||
register "reg_adv_ctrl3" = "0x00"
|
||||
register "reg_adv_ctrl4" = "0x00"
|
||||
register "reg_adv_ctrl5" = "0x05"
|
||||
register "reg_adv_ctrl6" = "0x00"
|
||||
register "reg_adv_ctrl7" = "0x00"
|
||||
register "reg_adv_ctrl8" = "0x00"
|
||||
register "reg_adv_ctrl9" = "0x00"
|
||||
register "reg_adv_ctrl10" = "0x5c"
|
||||
register "reg_adv_ctrl11" = "0x52"
|
||||
register "reg_adv_ctrl12" = "0xb5"
|
||||
register "reg_adv_ctrl13" = "0x00"
|
||||
register "reg_adv_ctrl14" = "0x80"
|
||||
register "reg_adv_ctrl15" = "0x0c"
|
||||
register "reg_adv_ctrl16" = "0x38"
|
||||
register "reg_adv_ctrl17" = "0x56"
|
||||
register "reg_adv_ctrl18" = "0x33"
|
||||
register "reg_adv_ctrl19" = "0xf0"
|
||||
register "reg_adv_ctrl20" = "0xf0"
|
||||
device i2c 2C on end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_hid" = ""INT3478""
|
||||
register "acpi_uid" = "0"
|
||||
register "acpi_name" = ""CAM1""
|
||||
register "chip_name" = ""imx 208 Camera""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
|
||||
|
||||
register "ssdb.lanes_used" = "2"
|
||||
register "ssdb.link_used" = "1"
|
||||
register "num_freq_entries" = "2"
|
||||
register "link_freq[0]" = "384 * MHz" # 384 MHz
|
||||
register "link_freq[1]" = "96 * MHz" # 96 MHz
|
||||
register "remote_name" = ""IPU0""
|
||||
|
||||
register "has_power_resource" = "1"
|
||||
#Controls
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_C3" #PP3300_FCAM_X
|
||||
register "gpio_panel.gpio[1].gpio_num" = "GPP_A17" #EN_UCAM_PWR
|
||||
register "gpio_panel.gpio[2].gpio_num" = "GPP_F20" #reset
|
||||
register "gpio_panel.gpio[3].gpio_num" = "GPP_H21" #CLK_EN
|
||||
|
||||
#_ON
|
||||
register "on_seq.ops_cnt" = "5"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(3, 0)"
|
||||
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
|
||||
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
|
||||
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
|
||||
register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
|
||||
|
||||
#_OFF
|
||||
register "off_seq.ops_cnt" = "4"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(3, 0)"
|
||||
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
|
||||
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
|
||||
register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 10 on
|
||||
probe UFC UFC_MIPI_IMX208
|
||||
end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_hid" = ""ACPI_DT_NAMESPACE_HID""
|
||||
register "acpi_uid" = "1"
|
||||
register "acpi_name" = ""NVM1""
|
||||
register "chip_name" = ""GT24C16S""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_NVM"
|
||||
|
||||
register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC""
|
||||
register "nvm_compat" = ""atmel,24c1024""
|
||||
|
||||
register "nvm_size" = "0x800"
|
||||
register "nvm_pagesize" = "0x01"
|
||||
register "nvm_readonly" = "0x01"
|
||||
register "nvm_width" = "0x08"
|
||||
|
||||
device i2c 50 on
|
||||
probe UFC UFC_MIPI_IMX208
|
||||
end
|
||||
end
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""GOOG0020""
|
||||
register "desc" = ""ChromeOS HPS""
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
|
||||
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
|
||||
# HPS uses I2C addresses 0x30 and 0x51.
|
||||
# The address we provide here is not significant because
|
||||
# neither coreboot nor Linux have a driver for HPS,
|
||||
# it's only used from userspace.
|
||||
device i2c 30 on
|
||||
probe HPS HPS_PRESENT
|
||||
end
|
||||
end
|
||||
end #I2C2
|
||||
device ref i2c3 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN9050""
|
||||
register "generic.desc" = ""ELAN Touchscreen""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
|
||||
register "generic.probed" = "1"
|
||||
register "generic.reset_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
|
||||
register "generic.reset_delay_ms" = "300"
|
||||
register "generic.reset_off_delay_ms" = "1"
|
||||
register "generic.enable_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
|
||||
register "generic.enable_delay_ms" = "6"
|
||||
register "generic.stop_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
|
||||
register "generic.stop_off_delay_ms" = "1"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 0x10 on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""GDIX0000""
|
||||
register "generic.desc" = ""Goodix Touchscreen""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
|
||||
register "generic.probed" = "1"
|
||||
register "generic.reset_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
|
||||
register "generic.reset_delay_ms" = "120"
|
||||
register "generic.reset_off_delay_ms" = "3"
|
||||
register "generic.enable_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
|
||||
register "generic.enable_delay_ms" = "12"
|
||||
register "generic.stop_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
|
||||
register "generic.stop_off_delay_ms" = "1"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 0x5d on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""SIS9815""
|
||||
register "generic.desc" = ""SIS Touchscreen""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
|
||||
register "generic.probed" = "1"
|
||||
register "generic.reset_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
|
||||
register "generic.stop_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
|
||||
register "generic.stop_delay_ms" = "100"
|
||||
register "generic.enable_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
|
||||
register "generic.enable_delay_ms" = "7"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "hid_desc_reg_offset" = "0x00"
|
||||
device i2c 5c on end
|
||||
end
|
||||
end #I2C3
|
||||
device ref i2c5 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
|
||||
register "wake" = "GPE0_DW2_14"
|
||||
register "probed" = "1"
|
||||
device i2c 15 on end
|
||||
end
|
||||
end #I2C5
|
||||
device ref hda on
|
||||
chip drivers/generic/max98357a
|
||||
register "hid" = ""MX98357A""
|
||||
register "sdmode_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
|
||||
register "sdmode_delay" = "5"
|
||||
device generic 0 on
|
||||
probe AUDIO MAX98357_ALC5682I_I2S
|
||||
end
|
||||
end
|
||||
|
||||
chip drivers/generic/max98357a
|
||||
register "hid" = ""MX98360A""
|
||||
register "sdmode_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
|
||||
register "sdmode_delay" = "5"
|
||||
device generic 0 on
|
||||
probe AUDIO MAX98360_ALC5682I_I2S
|
||||
end
|
||||
end
|
||||
|
||||
chip drivers/intel/soundwire
|
||||
device generic 0 on
|
||||
probe AUDIO MAX98373_ALC5682_SNDW
|
||||
chip drivers/soundwire/alc5682
|
||||
# SoundWire Link 0 ID 1
|
||||
register "desc" = ""Headset Codec""
|
||||
device generic 0.1 on end
|
||||
end
|
||||
chip drivers/soundwire/max98373
|
||||
# SoundWire Link 2 ID 3
|
||||
register "desc" = ""Left Speaker Amp""
|
||||
device generic 2.3 on end
|
||||
end
|
||||
chip drivers/soundwire/max98373
|
||||
# SoundWire Link 2 ID 7
|
||||
register "desc" = ""Right Speaker Amp""
|
||||
device generic 2.7 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref gspi1 on
|
||||
chip drivers/spi/acpi
|
||||
register "name" = ""CRFP""
|
||||
register "hid" = "ACPI_DT_NAMESPACE_HID"
|
||||
register "uid" = "1"
|
||||
register "compat_string" = ""google,cros-ec-spi""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
|
||||
register "wake" = "GPE0_DW2_15"
|
||||
device spi 0 on end
|
||||
end # FPMCU
|
||||
end
|
||||
device ref pch_espi on
|
||||
chip ec/google/chromeec
|
||||
use conn0 as mux_conn[0]
|
||||
use conn1 as mux_conn[1]
|
||||
use conn2 as mux_conn[2]
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
device ref pmc hidden
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port1 as usb2_port
|
||||
use tcss_usb3_port1 as usb3_port
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port2 as usb2_port
|
||||
use tcss_usb3_port2 as usb3_port
|
||||
device generic 1 alias conn1 on end
|
||||
end
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port3 as usb2_port
|
||||
use tcss_usb3_port3 as usb3_port
|
||||
device generic 2 alias conn2 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref tcss_xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C1 (DB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref tcss_usb3_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C2 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))"
|
||||
device ref tcss_usb3_port3 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C1 (DB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref usb2_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C2 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))"
|
||||
device ref usb2_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 WWAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port4 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Camera""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port6 on
|
||||
probe UFC UFC_USB
|
||||
end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A0 (DB)""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
|
||||
device ref usb2_port9 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
device ref usb2_port10 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A0 (DB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
|
||||
device ref usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 WWAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb3_port4 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <device/pci_ids.h>
|
||||
|
||||
const struct cpu_power_limits limits[] = {
|
||||
/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
|
||||
/* All values are for baseline config as per bug:191906315 comment #10 */
|
||||
{ PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 },
|
||||
{ PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 },
|
||||
{ PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 },
|
||||
{ PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 },
|
||||
{ PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 },
|
||||
};
|
||||
|
||||
void variant_devtree_update(void)
|
||||
{
|
||||
size_t total_entries = ARRAY_SIZE(limits);
|
||||
variant_update_power_limits(limits, total_entries);
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <chip.h>
|
||||
#include <fw_config.h>
|
||||
#include <baseboard/variants.h>
|
||||
|
||||
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
|
||||
{
|
||||
config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
|
||||
MAX98373_ALC5682_SNDW));
|
||||
}
|
||||
Loading…
Reference in New Issue