security/vboot: Deprecate VBOOT_VBNV_EC
Boards using VBOOT_VBNV_EC (nyan, daisy, veyron, peach_pit) are all ChromeOS devices and they've reached the end of life since Feb 2022. Therefore, remove VBOOT_VBNV_EC for them, each with different replacement. - nyan (nyan, nyan_big, nyan_blaze): Add RW_NVRAM to their FMAP (by reducing the size of RW_VPD), and replace VBOOT_VBNV_EC with VBOOT_VBNV_FLASH. - veyron: Add RW_NVRAM to their FMAP (by reducing the size of SHARED_DATA), and replace VBOOT_VBNV_EC with VBOOT_VBNV_FLASH. Also enlarge the OVERLAP_VERSTAGE_ROMSTAGE section for rk3288 (by reducing the size of PRERAM_CBMEM_CONSOLE), so that verstage won't exceed its allotted size. - daisy: Because BOOT_DEVICE_SPI_FLASH is not set, which is required for VBOOT_VBNV_FLASH, disable MAINBOARD_HAS_CHROMEOS and VBOOT configs. - peach_pit: As VBOOT is not set, simply remove the unused VBOOT_VBNV_EC option. Remove the VBOOT_VBNV_EC Kconfig option as well as related code, leaving VBOOT_VBNV_FLASH and VBOOT_VBNV_CMOS as the only two backend options for vboot nvdata (VBNV). Also add a check in read_vbnv() and save_vbnv() for VBNV options. BUG=b:178689388 TEST=util/abuild/abuild -t GOOGLE_NYAN -x -a TEST=util/abuild/abuild -t GOOGLE_VEYRON_JAQ -x -a TEST=util/abuild/abuild -t GOOGLE_DAISY -a TEST=util/abuild/abuild -t GOOGLE_PEACH_PIT -a BRANCH=none Change-Id: Ic67d69e694cff3176dbee12d4c6311bc85295863 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
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@ -176,7 +176,6 @@ CMOS, the EC, or in a read/write area of the SPI flash device.
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Select one of the following:
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* `VBOOT_VBNV_CMOS`
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* `VBOOT_VBNV_EC`
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* `VBOOT_VBNV_FLASH`
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More non-volatile storage features may be found in `security/vboot/Kconfig`.
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@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
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select EC_GOOGLE_CHROMEEC_I2C
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select BOARD_ROMSIZE_KB_4096
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select DRIVER_MAXIM_MAX77686
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select MAINBOARD_HAS_CHROMEOS
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select DRIVER_TI_TPS65090
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select MAINBOARD_FORCE_NATIVE_VGA_INIT
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@ -18,9 +17,6 @@ config BOARD_SPECIFIC_OPTIONS
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select I2C_TPM
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select MAINBOARD_HAS_TPM1
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config VBOOT
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select VBOOT_VBNV_EC
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config MAINBOARD_DIR
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default "google/daisy"
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@ -18,7 +18,7 @@ config BOARD_SPECIFIC_OPTIONS
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config VBOOT
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select VBOOT_VBNV_EC
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select VBOOT_VBNV_FLASH
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config MAINBOARD_DIR
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default "google/nyan"
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@ -23,6 +23,7 @@ FLASH@0x0 0x400000 {
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FW_MAIN_B(CBFS)@0x2000 0x75f00
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RW_FWID_B@0x77f00 0x100
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}
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RW_VPD(PRESERVE)@0x2f8000 0x8000
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RW_VPD(PRESERVE)@0x2f8000 0x4000
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RW_NVRAM(PRESERVE)@0x2fc000 0x4000
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RW_LEGACY(CBFS)@0x300000 0x100000
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}
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@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS
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config VBOOT
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select VBOOT_VBNV_EC
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select VBOOT_VBNV_FLASH
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config MAINBOARD_DIR
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default "google/nyan_big"
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@ -23,6 +23,7 @@ FLASH@0x0 0x400000 {
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FW_MAIN_B(CBFS)@0x2000 0x75f00
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RW_FWID_B@0x77f00 0x100
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}
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RW_VPD(PRESERVE)@0x2f8000 0x8000
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RW_VPD(PRESERVE)@0x2f8000 0x4000
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RW_NVRAM(PRESERVE)@0x2fc000 0x4000
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RW_LEGACY(CBFS)@0x300000 0x100000
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}
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@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS
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config VBOOT
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select VBOOT_VBNV_EC
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select VBOOT_VBNV_FLASH
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config MAINBOARD_DIR
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default "google/nyan_blaze"
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@ -23,6 +23,7 @@ FLASH@0x0 0x400000 {
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FW_MAIN_B(CBFS)@0x2000 0x75f00
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RW_FWID_B@0x77f00 0x100
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}
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RW_VPD(PRESERVE)@0x2f8000 0x8000
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RW_VPD(PRESERVE)@0x2f8000 0x4000
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RW_NVRAM(PRESERVE)@0x2fc000 0x4000
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RW_LEGACY(CBFS)@0x300000 0x100000
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}
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@ -17,9 +17,6 @@ config BOARD_SPECIFIC_OPTIONS
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select MAINBOARD_HAS_TPM1
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select MISSING_BOARD_RESET
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config VBOOT
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select VBOOT_VBNV_EC
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config MAINBOARD_DIR
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default "google/peach_pit"
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@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS
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select MAINBOARD_HAS_TPM1
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config VBOOT
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select VBOOT_VBNV_EC
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select VBOOT_VBNV_FLASH
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config MAINBOARD_DIR
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default "google/veyron"
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@ -14,9 +14,10 @@ FLASH@0x0 0x400000 {
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FW_MAIN_A(CBFS)@0x2000 0x75f00
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RW_FWID_A@0x77f00 0x100
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}
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RW_SHARED@0x278000 0x4000 {
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SHARED_DATA@0x0 0x4000
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RW_SHARED@0x278000 0x2000 {
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SHARED_DATA@0x0 0x2000
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}
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RW_NVRAM(PRESERVE)@0x27a000 0x2000
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RW_ELOG(PRESERVE)@0x27c000 0x4000
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RW_SECTION_B@0x280000 0x78000 {
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VBLOCK_B@0x0 0x2000
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@ -58,12 +58,6 @@ config VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
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Vboot non-volatile storage data will be backed up from CMOS to flash
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and restored from flash if the CMOS is invalid due to power loss.
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config VBOOT_VBNV_EC
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bool
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default n
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help
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VBNV is stored in EC
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config VBOOT_VBNV_FLASH
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bool
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default n
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@ -72,11 +72,6 @@ verstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c
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romstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c
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ramstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c
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bootblock-$(CONFIG_VBOOT_VBNV_EC) += vbnv_ec.c
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verstage-$(CONFIG_VBOOT_VBNV_EC) += vbnv_ec.c
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romstage-$(CONFIG_VBOOT_VBNV_EC) += vbnv_ec.c
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ramstage-$(CONFIG_VBOOT_VBNV_EC) += vbnv_ec.c
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bootblock-$(CONFIG_VBOOT_VBNV_FLASH) += vbnv_flash.c
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verstage-$(CONFIG_VBOOT_VBNV_FLASH) += vbnv_flash.c
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romstage-$(CONFIG_VBOOT_VBNV_FLASH) += vbnv_flash.c
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@ -1,5 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <string.h>
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#include <types.h>
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#include <security/vboot/vbnv.h>
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@ -61,10 +62,10 @@ void read_vbnv(uint8_t *vbnv_copy)
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{
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if (CONFIG(VBOOT_VBNV_CMOS))
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read_vbnv_cmos(vbnv_copy);
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else if (CONFIG(VBOOT_VBNV_EC))
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read_vbnv_ec(vbnv_copy);
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else if (CONFIG(VBOOT_VBNV_FLASH))
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read_vbnv_flash(vbnv_copy);
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else
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dead_code();
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/* Check data for consistency */
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if (!verify_vbnv(vbnv_copy))
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@ -79,10 +80,10 @@ void save_vbnv(const uint8_t *vbnv_copy)
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{
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if (CONFIG(VBOOT_VBNV_CMOS))
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save_vbnv_cmos(vbnv_copy);
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else if (CONFIG(VBOOT_VBNV_EC))
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save_vbnv_ec(vbnv_copy);
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else if (CONFIG(VBOOT_VBNV_FLASH))
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save_vbnv_flash(vbnv_copy);
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else
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dead_code();
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/* Clear initialized flag to force cached data to be updated */
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vbnv_initialized = 0;
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@ -1,17 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <types.h>
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#include <ec/google/chromeec/ec.h>
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#include <security/vboot/vbnv.h>
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#include <security/vboot/vbnv_layout.h>
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void read_vbnv_ec(uint8_t *vbnv_copy)
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{
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google_chromeec_vbnv_context(1, vbnv_copy, VBOOT_VBNV_BLOCK_SIZE);
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}
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void save_vbnv_ec(const uint8_t *vbnv_copy)
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{
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google_chromeec_vbnv_context(0, (uint8_t *)vbnv_copy,
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VBOOT_VBNV_BLOCK_SIZE);
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}
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@ -18,9 +18,9 @@ SECTIONS
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SRAM_START(0xFF700000)
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TTB(0xFF700000, 16K)
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BOOTBLOCK(0xFF704004, 16K - 4)
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PRERAM_CBMEM_CONSOLE(0xFF708000, 2K)
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VBOOT2_WORK(0xFF708800, 12K)
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OVERLAP_VERSTAGE_ROMSTAGE(0xFF70B800, 46K + 768)
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PRERAM_CBMEM_CONSOLE(0xFF708000, 1K)
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VBOOT2_WORK(0xFF708400, 12K)
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OVERLAP_VERSTAGE_ROMSTAGE(0xFF70B400, 47K + 768)
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PRERAM_CBFS_CACHE(0xFF717300, 256)
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TIMESTAMP(0xFF717400, 0x180)
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STACK(0xFF717580, 3K - 0x180)
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