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soc/amd/common/include/spi: add Cezanne-specific comment 

The Cezanne PPR #56569 Rev 3.03 has one more SPI FIFO bytes defined
compared to the previous generations. It is unclear if adding some
special handling for Cezanne would be worth the effort, since the
current code just doesn't use the last byte which should be safe to do,
since this only affects the maximum number of bytes that can be used for
one SPI transaction. Having another byte to use on Cezanne wouldn't
reduce the number of SPI transactions to write a 256 byte data block.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic730f4fe838f59066120c811833995c132c84c1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-12-10 18:38:16 +01:00
parent 601a971545
commit 6b0f45199c
1 changed files with 1 additions and 1 deletions
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src/soc/amd/common/block/include/amdblocks/spi.h
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@ -71,7 +71,7 @@ enum spi100_speed {
#define SPI_RD4DW_EN_HOST BIT(15) #define SPI_RD4DW_EN_HOST BIT(15)
#define SPI_FIFO 0x80 #define SPI_FIFO 0x80
#define SPI_FIFO_LAST_BYTE 0xc6 #define SPI_FIFO_LAST_BYTE 0xc6 /* 0xc7 for Cezanne */
#define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO + 1) #define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO + 1)
struct spi_config { struct spi_config {