soc/intel/skylake: Add option to enable/disable EIST
Set MSR 0x1A0 bit[16] based on EIST config option. Default Hardware Managed P-state (HWP) also known as Intel Speed Shift is enabled on SKL hence disable EIST and ACPI P-state table. Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -523,9 +523,10 @@ void generate_cpu_entries(device_t device)
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generate_c_state_entries(is_s0ix_enable,
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max_c_state);
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/* Generate P-state tables */
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generate_p_state_entries(core_id,
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cores_per_package);
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if (config->eist_enable)
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/* Generate P-state tables */
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generate_p_state_entries(core_id,
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cores_per_package);
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acpigen_pop_len();
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}
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@ -459,6 +459,12 @@ struct soc_intel_skylake_config {
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/* Enable SGX feature */
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u8 sgx_enable;
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/* Enable/Disable EIST
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* 1b - Enabled
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* 0b - Disabled
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*/
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u8 eist_enable;
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};
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typedef struct soc_intel_skylake_config config_t;
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@ -261,6 +261,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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/* Enable PMC XRAM read */
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tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable;
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/* Enable/Disable EIST */
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tconfig->Eist = config->eist_enable;
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soc_irq_settings(params);
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}
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@ -245,12 +245,17 @@ static void configure_isst(void)
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static void configure_misc(void)
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{
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device_t dev = SA_DEV_ROOT;
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config_t *conf = dev->chip_info;
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msr_t msr;
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msr = rdmsr(IA32_MISC_ENABLE);
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msr.lo |= (1 << 0); /* Fast String enable */
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msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
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msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
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if (conf->eist_enable)
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msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
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else
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msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */
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wrmsr(IA32_MISC_ENABLE, msr);
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/* Disable Thermal interrupts */
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