soc/intel/skylake: Add option to enable/disable EIST

Set MSR 0x1A0 bit[16] based on EIST config option.
Default Hardware Managed P-state (HWP) also known as Intel Speed Shift
is enabled on SKL hence disable EIST and ACPI P-state table.

Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/soc/intel/skylake/acpi.c

@@ -523,6 +523,7 @@ void generate_cpu_entries(device_t device)
 			generate_c_state_entries(is_s0ix_enable,
 				max_c_state);
 
+			if (config->eist_enable)
 				/* Generate P-state tables */
 				generate_p_state_entries(core_id,
 						cores_per_package);

src/soc/intel/skylake/chip.h

@@ -459,6 +459,12 @@ struct soc_intel_skylake_config {
 
 	/* Enable SGX feature */
 	u8 sgx_enable;
+
+	/* Enable/Disable EIST
+	 * 1b - Enabled
+	 * 0b - Disabled
+	 */
+	u8 eist_enable;
 };
 
 typedef struct soc_intel_skylake_config config_t;

src/soc/intel/skylake/chip_fsp20.c

@@ -261,6 +261,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	/* Enable PMC XRAM read */
 	tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable;
 
+	/* Enable/Disable EIST */
+	tconfig->Eist = config->eist_enable;
+
 	soc_irq_settings(params);
 }
 

src/soc/intel/skylake/cpu.c

@@ -245,12 +245,17 @@ static void configure_isst(void)
 
 static void configure_misc(void)
 {
+	device_t dev = SA_DEV_ROOT;
+	config_t *conf = dev->chip_info;
 	msr_t msr;
 
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= (1 << 0);	/* Fast String enable */
 	msr.lo |= (1 << 3);	/* TM1/TM2/EMTTM enable */
+	if (conf->eist_enable)
 		msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
+	else
+		msr.lo &= ~(1 << 16);	/* Enhanced SpeedStep Disable */
 	wrmsr(IA32_MISC_ENABLE, msr);
 
 	/* Disable Thermal interrupts */