soc/amd: factor out PM_DECODE_EN register definitions

Change-Id: I005709a8780725339e7c08fbfff94e89c8ef26da
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/soc/amd/common/block/include/amdblocks/acpimmio.h

@@ -10,6 +10,17 @@
 #define PM_INDEX			0xcd6
 #define PM_DATA				0xcd7
 
+/*
+ * Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7. Valid for Mullins and
+ * newer SoCs, but not for the generations with separate FCH or Kabini.
+ */
+#define PM_DECODE_EN			0x00
+#define   SMBUS_ASF_IO_EN		(1 << 4)
+#define   CF9_IO_EN			(1 << 1)
+#define   LEGACY_IO_EN			(1 << 0)
+
+#define SMB_ASF_IO_BASE			0x01 /* part of PM_DECODE_EN */
+
 /*
  * Earlier devices enable the ACPIMMIO bank decodes in PMx24. All discrete FCHs
  * and the Kabini SoC fall into this category. Kabini's successor, Mullins, uses

src/soc/amd/picasso/include/soc/southbridge.h

@@ -22,11 +22,6 @@
 #define   SMB_UART_1_8M_SHIFT		28
 
 /* Power management registers:  0xfed80300 or index/data at IO 0xcd6/cd7 */
-#define PM_DECODE_EN			0x00
-#define   SMBUS_ASF_IO_EN		BIT(4)
-#define   CF9_IO_EN			BIT(1)
-#define   LEGACY_IO_EN			BIT(0)
-#define SMB_ASF_IO_BASE			0x01 /* part of PM_DECODE_EN in PPR */
 #define PM_PCI_CTRL			0x08
 #define   FORCE_SLPSTATE_RETRY		BIT(25)
 

src/soc/amd/stoneyridge/include/soc/southbridge.h

@@ -15,15 +15,10 @@
  */
 
 /* Power management registers:  0xfed80300 or index/data at IO 0xcd6/cd7 */
-#define PM_DECODE_EN			0x00
-#define   CF9_IO_EN			BIT(1)
-#define   LEGACY_IO_EN			BIT(0)
 #define PM_PCI_CTRL			0x08
 #define   FORCE_SLPSTATE_RETRY		BIT(25)
 #define   FORCE_STPCLK_RETRY		BIT(24)
 
-#define SMB_ASF_IO_BASE			0x01 /* part of PM_DECODE_EN */
-
 #define PWR_RESET_CFG			0x10
 #define   TOGGLE_ALL_PWR_GOOD		BIT(1)