Revert "mb/google/skyrim: Create whiterun variant"
For simplicity, OEM devices are given a single codename per build variant. Winterhold was intended to be the lead device and was chosen as the code name for this OEM. Unfortunately, Winterhold was cancelled. We attempted to rename Winterhold to Whiterun to avoid future confusion. Again, unfortunately, since some devices were already built, changing the name requires a manual change to force the firmware to be taken by the DUT. This was not a reasonable path forward, so we're abandoning the naming to Whiterun.
This reverts commit af69de494e.
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Idef95f0f4f369b235937e1806ce57c427e441f21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73583
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Jon Murphy
Eric Lai
parent
599052942c
commit
6b6b8f86df
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@ -87,7 +87,6 @@ config SPL_RW_AB_TABLE_FILE
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default "3rdparty/blobs/mainboard/google/skyrim/TypeId0x55_SplTableBl_MDN_CHROME.sbin"
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config SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL
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default y if BOARD_GOOGLE_WHITERUN
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default y if BOARD_GOOGLE_WINTERHOLD
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default n
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@ -103,7 +102,6 @@ config MAINBOARD_FAMILY
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config MAINBOARD_PART_NUMBER
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default "Skyrim" if BOARD_GOOGLE_SKYRIM
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default "Whiterun" if BOARD_GOOGLE_WHITERUN
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default "Winterhold" if BOARD_GOOGLE_WINTERHOLD
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default "Frostflow" if BOARD_GOOGLE_FROSTFLOW
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default "Crystaldrift" if BOARD_GOOGLE_CRYSTALDRIFT
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@ -116,7 +114,6 @@ config OVERRIDE_DEVICETREE
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config VARIANT_DIR
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string
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default "skyrim" if BOARD_GOOGLE_SKYRIM
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default "whiterun" if BOARD_GOOGLE_WHITERUN
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default "winterhold" if BOARD_GOOGLE_WINTERHOLD
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default "frostflow" if BOARD_GOOGLE_FROSTFLOW
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default "crystaldrift" if BOARD_GOOGLE_CRYSTALDRIFT
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@ -5,12 +5,6 @@ config BOARD_GOOGLE_SKYRIM
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select BOARD_GOOGLE_BASEBOARD_SKYRIM
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select SOC_AMD_COMMON_BLOCK_ACPI_DPTC
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config BOARD_GOOGLE_WHITERUN
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bool "-> Whiterun"
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select BOARD_GOOGLE_BASEBOARD_SKYRIM
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select SOC_AMD_COMMON_BLOCK_ACPI_DPTC
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select FEATURE_DYNAMIC_DPTC
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config BOARD_GOOGLE_WINTERHOLD
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bool "-> Winterhold"
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select BOARD_GOOGLE_BASEBOARD_SKYRIM
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@ -1,5 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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subdirs-y += ./memory
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ramstage-y += gpio.c
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@ -1,28 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <gpio.h>
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/* GPIO configuration in ramstage */
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static const struct soc_amd_gpio override_gpio_table[] = {
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/* SOC_PEN_DETECT_ODL */
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PAD_NC(GPIO_3),
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/* EN_PWR_WWAN_X */
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PAD_NC(GPIO_8),
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/* SD_AUX_RST_SOC_L */
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PAD_NC(GPIO_27),
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/* WWAN_RST_L */
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PAD_NC(GPIO_42),
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};
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void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size)
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{
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*size = ARRAY_SIZE(override_gpio_table);
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*gpio = override_gpio_table;
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}
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@ -1,116 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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External(\_SB.DTTB, MethodObj)
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External(\_SB.DTTC, MethodObj)
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External(\_SB.DTTD, MethodObj)
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External(\_SB.DTTE, MethodObj)
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External(\_SB.DTTF, MethodObj)
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Scope (\_SB)
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{
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//---------------------------------------------
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// Table | A | B | C | D | E | F | First boot |
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//---------------------------------------------
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// PRTN | 0 | 1 | 2 | 3 | 4 | 5 | 7 |
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//---------------------------------------------
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Name (PRTN, 7)
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Method (DTTS, 0, Serialized)
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{
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// Set table A as default table after power on device
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If (\_SB.PRTN == 7)
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{
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\_SB.DDEF()
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\_SB.PRTN = 0
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Return (0)
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}
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If (\_SB.PCI0.LPCB.EC0.STTB == 0) { // Desktop
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If (\_SB.PCI0.LPCB.EC0.LIDS == 1) { // Lid-open
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// Table A/B
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If ((\_SB.PRTN == 0) || (\_SB.PRTN == 1)) {
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// AMB sensor trigger point
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// 50C will store 123(0x7B) in mapped memory
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// 50C=323K, 323-200(offset)=123(0x7B)
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If (\_SB.PCI0.LPCB.EC0.TIN4 >= 123) {
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\_SB.DTTB()
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\_SB.PRTN = 1
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Return (0)
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}
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// AMB sensor release point
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If ((\_SB.PCI0.LPCB.EC0.TIN4 <= 118)) {
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\_SB.DDEF()
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\_SB.PRTN = 0
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Return (0)
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}
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// Keep tht previous thermal table
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Return (0)
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} Else {
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If (\_SB.PRTN == 3 || \_SB.PRTN == 5) {
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\_SB.DTTB()
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\_SB.PRTN = 1
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Return (0)
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} Else {
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\_SB.DDEF()
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\_SB.PRTN = 0
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Return (0)
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}
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}
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} Else { // Lid-close
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// Table C/D
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If (\_SB.PRTN == 2 || \_SB.PRTN == 3) {
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If (\_SB.PCI0.LPCB.EC0.TIN4 >= 128) {
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\_SB.DTTD()
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\_SB.PRTN = 3
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Return (0)
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}
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If(\_SB.PCI0.LPCB.EC0.TIN4 <= 123) {
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\_SB.DTTC()
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\_SB.PRTN = 2
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Return (0)
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}
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// Keep tht previous thermal table
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Return (0)
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} Else {
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If (\_SB.PRTN == 1 || \_SB.PRTN == 5) {
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\_SB.DTTD()
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\_SB.PRTN = 3
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Return (0)
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} Else {
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\_SB.DTTC()
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\_SB.PRTN = 2
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Return (0)
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}
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}
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}
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} Else { // Laptop
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// Table E/F
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If (\_SB.PRTN == 4 || \_SB.PRTN == 5) {
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// AMB sensor trigger point
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If (\_SB.PCI0.LPCB.EC0.TIN4 >= 118) {
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\_SB.DTTF()
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\_SB.PRTN = 5
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Return (0)
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}
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// AMB sensor release point
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If ((\_SB.PCI0.LPCB.EC0.TIN4 <= 113)) {
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\_SB.DTTE()
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\_SB.PRTN = 4
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Return (0)
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}
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// Keep tht previous thermal table
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Return (0)
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} Else {
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If (\_SB.PRTN == 1 || \_SB.PRTN == 3) {
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\_SB.DTTF()
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\_SB.PRTN = 5
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Return (0)
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} Else {
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\_SB.DTTE()
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\_SB.PRTN = 4
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Return (0)
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}
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}
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} // Desktop/Laptop End
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}
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}
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@ -1,3 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/ec.h>
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@ -1,14 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# This is an auto-generated file. Do not edit!!
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# Generated by:
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# util/spd_tools/bin/part_id_gen MDN lp5 src/mainboard/google/skyrim/variants/whiterun/memory src/mainboard/google/skyrim/variants/whiterun/memory/mem_parts_used.txt
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SPD_SOURCES =
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SPD_SOURCES += spd/lp5/set-1/spd-5.hex # ID = 0(0b0000) Parts = K3LKLKL0EM-MGCN
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SPD_SOURCES += spd/lp5/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
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SPD_SOURCES += spd/lp5/set-1/spd-3.hex # ID = 2(0b0010) Parts = K3LKBKB0BM-MGCP, H58G56AK6BX069
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SPD_SOURCES += spd/lp5/set-1/spd-2.hex # ID = 3(0b0011) Parts = MT62F1G32D4DR-031 WT:B
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SPD_SOURCES += spd/lp5/set-1/spd-7.hex # ID = 4(0b0100) Parts = MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT, H58G56BK7BX068
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SPD_SOURCES += spd/lp5/set-1/spd-6.hex # ID = 5(0b0101) Parts = K3LKCKC0BM-MGCP, H58G66AK6BX070
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SPD_SOURCES += spd/lp5/set-1/spd-4.hex # ID = 6(0b0110) Parts = MT62F2G32D8DR-031 WT:B
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SPD_SOURCES += spd/lp5/set-1/spd-8.hex # ID = 7(0b0111) Parts = MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT, H58G66BK7BX067
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@ -1,21 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# This is an auto-generated file. Do not edit!!
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# Generated by:
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# util/spd_tools/bin/part_id_gen MDN lp5 src/mainboard/google/skyrim/variants/whiterun/memory src/mainboard/google/skyrim/variants/whiterun/memory/mem_parts_used.txt
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DRAM Part Name ID to assign
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K3LKLKL0EM-MGCN 0 (0000)
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MT62F512M32D2DR-031 WT:B 1 (0001)
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H9JCNNNBK3MLYR-N6E 1 (0001)
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K3LKBKB0BM-MGCP 2 (0010)
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H58G56AK6BX069 2 (0010)
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MT62F1G32D4DR-031 WT:B 3 (0011)
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MT62F1G32D2DS-026 WT:B 4 (0100)
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K3KL8L80CM-MGCT 4 (0100)
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K3LKCKC0BM-MGCP 5 (0101)
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H58G66AK6BX070 5 (0101)
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MT62F2G32D8DR-031 WT:B 6 (0110)
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MT62F2G32D4DS-026 WT:B 7 (0111)
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K3KL9L90CM-MGCT 7 (0111)
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H58G56BK7BX068 4 (0100)
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H58G66BK7BX067 7 (0111)
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@ -1,15 +0,0 @@
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K3LKLKL0EM-MGCN,
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MT62F512M32D2DR-031 WT:B,
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H9JCNNNBK3MLYR-N6E,
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K3LKBKB0BM-MGCP,
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H58G56AK6BX069,
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MT62F1G32D4DR-031 WT:B,
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MT62F1G32D2DS-026 WT:B,
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K3KL8L80CM-MGCT,
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K3LKCKC0BM-MGCP,
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H58G66AK6BX070,
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MT62F2G32D8DR-031 WT:B,
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MT62F2G32D4DS-026 WT:B,
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K3KL9L90CM-MGCT,
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H58G56BK7BX068,
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H58G66BK7BX067,
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@ -1,261 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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fw_config
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field FP 0
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option FP_ABSENT 0
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option FP_PRESENT 1
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end
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end
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chip soc/amd/mendocino
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# Set DPTC multi-profile common parameters
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# Refer the spec "FT6 Infrastructure Roadmap"#57316
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# Set system_configuration to 4 for 15W
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register "system_configuration" = "4"
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register "thermctl_limit_degreeC" = "97"
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register "stt_control" = "1"
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register "stt_pcb_sensor_count" = "2"
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register "stt_alpha_apu" = "0x199A"
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register "stt_error_coeff" = "0x21"
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register "stt_error_rate_coefficient" = "0xCCD"
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# These registers are defined in AMD DevHub document #57316.
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# Normal
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register "vrm_current_limit_mA" = "28000"
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register "vrm_maximum_current_limit_mA" = "50000"
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register "vrm_soc_current_limit_mA" = "10000"
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# Throttle (e.g., Low/No Battery)
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register "vrm_current_limit_throttle_mA" = "20000"
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register "vrm_maximum_current_limit_throttle_mA" = "20000"
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register "vrm_soc_current_limit_throttle_mA" = "10000"
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# Set Dynamic DPTC thermal profile Table A (Default)
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register "fast_ppt_limit_mW" = "30000"
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register "slow_ppt_limit_mW" = "18000"
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register "slow_ppt_time_constant_s" = "7"
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register "stt_min_limit" = "7000"
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register "stt_m1" = "0x148"
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register "stt_m2" = "0x38F"
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register "stt_c_apu" = "0xDF9A"
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register "stt_skin_temp_apu" = "0x3200"
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# Set Dynamic DPTC thermal profile confiuration. Table B
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register "fast_ppt_limit_mW_B" = "20000"
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register "slow_ppt_limit_mW_B" = "13000"
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register "slow_ppt_time_constant_s_B" = "5"
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register "stt_min_limit_B" = "5000"
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register "stt_m1_B" = "0x11F"
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register "stt_m2_B" = "0x3AE"
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register "stt_c_apu_B" = "0xE19A"
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register "stt_skin_temp_apu_B" = "0x3400"
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# Set Dynamic DPTC thermal profile confiuration. Table C
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register "fast_ppt_limit_mW_C" = "30000"
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register "slow_ppt_limit_mW_C" = "22000"
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register "slow_ppt_time_constant_s_C" = "10"
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register "stt_min_limit_C" = "10000"
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register "stt_m1_C" = "0x1A4"
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register "stt_m2_C" = "0x2E1"
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register "stt_c_apu_C" = "0xDACD"
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register "stt_skin_temp_apu_C" = "0x3600"
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# Set Dynamic DPTC thermal profile confiuration. Table D
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register "fast_ppt_limit_mW_D" = "25000"
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register "slow_ppt_limit_mW_D" = "15000"
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register "slow_ppt_time_constant_s_D" = "8"
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register "stt_min_limit_D" = "8000"
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register "stt_m1_D" = "0x1C3"
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register "stt_m2_D" = "0x2BB"
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register "stt_c_apu_D" = "0xDE00"
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register "stt_skin_temp_apu_D" = "0x3800"
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# Set Dynamic DPTC thermal profile confiuration. Table E
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register "fast_ppt_limit_mW_E" = "22000"
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register "slow_ppt_limit_mW_E" = "15000"
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register "slow_ppt_time_constant_s_E" = "4"
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register "stt_min_limit_E" = "7000"
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register "stt_m1_E" = "0x114"
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register "stt_m2_E" = "0x371"
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register "stt_c_apu_E" = "0xE333"
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register "stt_skin_temp_apu_E" = "0x3000"
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# Set Dynamic DPTC thermal profile confiuration. Table F
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register "fast_ppt_limit_mW_F" = "18000"
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register "slow_ppt_limit_mW_F" = "12000"
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register "slow_ppt_time_constant_s_F" = "2"
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register "stt_min_limit_F" = "5000"
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register "stt_m1_F" = "0x15C"
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register "stt_m2_F" = "0x33D"
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register "stt_c_apu_F" = "0xE866"
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register "stt_skin_temp_apu_F" = "0x3200"
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register "i2c[0]" = "{
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.speed = I2C_SPEED_FAST,
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.speed_config[0] = {
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||||
.speed = I2C_SPEED_FAST,
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.scl_hcnt = 107,
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.scl_lcnt = 230,
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.sda_hold = 100
|
||||
}
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||||
}"
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||||
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||||
device domain 0 on
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||||
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register "dxio_tx_vboost_enable" = "1"
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device ref gpp_bridge_1 on
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||||
# Required so the NVMe gets placed into D3 when entering S0i3.
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chip drivers/pcie/rtd3/device
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register "name" = ""NVME""
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device pci 00.0 on end
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||||
end
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||||
end # eMMC
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||||
device ref gpp_bridge_2 on
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||||
# Required so the NVMe gets placed into D3 when entering S0i3.
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chip drivers/pcie/rtd3/device
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register "name" = ""NVME""
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device pci 00.0 on end
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||||
end
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||||
end # NVMe
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||||
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||||
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
|
||||
device ref xhci_1 on # XHCI1 controller
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||||
chip drivers/usb/acpi
|
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device ref xhci_1_root_hub on # XHCI1 root hub
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||||
chip drivers/usb/acpi
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device ref usb3_port3 on # USB 3.1 port3
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chip drivers/usb/acpi
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||||
register "desc" = ""USB3 Type-A Port A0 (MLB)""
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||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))"
|
||||
device usb 3.2 on end
|
||||
end
|
||||
end # USB 3.1 port3
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
device ref usb2_port3 on # USB 2 port3
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A0 (MLB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))"
|
||||
device usb 2.2 on end
|
||||
end
|
||||
end # USB 2 port3
|
||||
end
|
||||
end # XHCI1 root hub
|
||||
end
|
||||
end # XHCI1 controller
|
||||
end # Internal GPP Bridge 0 to Bus A
|
||||
end # domain
|
||||
|
||||
device ref i2c_0 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)"
|
||||
register "wake" = "GEVENT_20"
|
||||
register "detect" = "1"
|
||||
device i2c 15 on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""GXTP7863""
|
||||
register "generic.desc" = ""Goodix Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)"
|
||||
register "generic.wake" = "GEVENT_20"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 2c on end
|
||||
end
|
||||
end # I2C0
|
||||
device ref i2c_1 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN900C""
|
||||
register "generic.desc" = ""ELAN Touchscreen""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)"
|
||||
register "generic.detect" = "1"
|
||||
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)"
|
||||
register "generic.enable_delay_ms" = "10"
|
||||
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)"
|
||||
register "generic.reset_off_delay_ms" = "1"
|
||||
register "generic.reset_delay_ms" = "10"
|
||||
register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)"
|
||||
register "generic.stop_delay_ms" = "180"
|
||||
register "generic.stop_off_delay_ms" = "1"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 10 on end
|
||||
end
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""MLFS0000""
|
||||
register "desc" = ""Melfas Touchscreen""
|
||||
register "detect" = "1"
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_29)"
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)"
|
||||
register "enable_delay_ms" = "1"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)"
|
||||
register "reset_delay_ms" = "20"
|
||||
register "reset_off_delay_ms" = "2"
|
||||
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)"
|
||||
register "stop_off_delay_ms" = "2"
|
||||
register "has_power_resource" = "1"
|
||||
device i2c 34 on end
|
||||
end
|
||||
end # I2C1
|
||||
device ref i2c_2 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""RTL5682""
|
||||
register "name" = ""RT58""
|
||||
register "desc" = ""Realtek RT5682""
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)"
|
||||
register "property_count" = "1"
|
||||
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||
register "property_list[0].name" = ""realtek,jd-src""
|
||||
register "property_list[0].integer" = "1"
|
||||
device i2c 1a on end
|
||||
end
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""10EC1019""
|
||||
register "desc" = ""Realtek SPK AMP R""
|
||||
register "uid" = "1"
|
||||
device i2c 29 on end
|
||||
end
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""10EC1019""
|
||||
register "desc" = ""Realtek SPK AMP L""
|
||||
register "uid" = "2"
|
||||
register "probed" = "1"
|
||||
device i2c 2a on end
|
||||
end
|
||||
end # I2C2
|
||||
|
||||
device ref uart_1 on
|
||||
chip drivers/uart/acpi
|
||||
register "name" = ""CRFP""
|
||||
register "desc" = ""Fingerprint Reader""
|
||||
register "hid" = "ACPI_DT_NAMESPACE_HID"
|
||||
register "compat_string" = ""google,cros-ec-uart""
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_24)"
|
||||
register "wake" = "GEVENT_15"
|
||||
register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)"
|
||||
register "has_power_resource" = "1"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_12)"
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_4)"
|
||||
register "enable_delay_ms" = "3"
|
||||
device generic 0 alias fpmcu on
|
||||
probe FP FP_PRESENT
|
||||
end
|
||||
end
|
||||
end # UART1
|
||||
|
||||
end # chip soc/amd/mendocino
|
||||
Loading…
Reference in New Issue