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mb/sapphire/pureplatinumh61: Don't write BUC and beyond 

The BUC register is actually only 8 bits wide and setting bit 5
(disabling GbE) is already done by generic code.

Change-Id: I729a2a28f4b0d94eddd070dc89b7341ac0c35e4a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Nico Huber 2019-11-17 01:45:50 +01:00 committed by Patrick Georgi
parent 25128a7997
commit 6b7b016b60
1 changed files with 0 additions and 5 deletions
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5
src/mainboard/sapphire/pureplatinumh61/early_init.c
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@ -26,11 +26,6 @@ void mainboard_pch_lpc_setup(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
} }
void mainboard_late_rcba_config(void)
{
/* Disable devices. */
RCBA32(0x3414) = 0x00000020;
}
const struct southbridge_usb_port mainboard_usb_ports[] = { const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 0 }, { 1, 0, 0 },
{ 1, 0, 0 }, { 1, 0, 0 },