soc/qualcomm/sc7280: Add SocInfo support in coreboot
Add support for SocInfo in coreboot. The API socinfo_modem_supported is added to help to differentiate between LTE and WiFi SKUs. BUG=b:232302324 TEST=Validate boards are detected correctly on LTE and Wifi SKUs Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Change-Id: I61047ad49772c3796ba403cafde311ad184a4093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
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@ -7,6 +7,7 @@ all-y += ../common/timer.c
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all-y += ../common/gpio.c
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all-y += ../common/clock.c
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all-y += clock.c
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all-y += socinfo.c
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all-y += ../common/spi.c
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all-$(CONFIG_SC7280_QSPI) += ../common/qspi.c
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all-y += ../common/qupv3_config.c
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@ -0,0 +1,59 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/**
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Chip identification type. Any new ids must be added to the end.
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*/
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typedef enum{
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CHIPINFO_ID_UNKNOWN = 0,
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CHIPINFO_ID_SM_KODIAK = 475,
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CHIPINFO_ID_SC_KODIAK_CHROME = 487,
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CHIPINFO_ID_SC_7CPLUSGEN3 = CHIPINFO_ID_SC_KODIAK_CHROME,
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CHIPINFO_ID_SC_KODIAK_WINDOWS = 488,
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CHIPINFO_ID_QCM_KODIAK = 497,
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CHIPINFO_ID_QCS_KODIAK = 498,
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CHIPINFO_ID_SMP_KODIAK = 499,
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CHIPINFO_ID_SM_KODIAK_LTE_ONLY = 515,
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CHIPINFO_ID_SCP_KODIAK = 546,
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CHIPINFO_ID_SCP_7CPLUSGEN3 = CHIPINFO_ID_SCP_KODIAK,
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CHIPINFO_ID_SC_8CGEN3 = 553,
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CHIPINFO_ID_SCP_8CGEN3 = 563,
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CHIPINFO_ID_KODIAK_SCP_7CGEN3 = 567,
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CHIPINFO_ID_QCS_KODIAK_LITE = 575,
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CHIPINFO_ID_QCM_KODIAK_LITE = 576,
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CHIPINFO_NUM_IDS,
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CHIPINFO_ID_32BITS = 0x7FFFFFF
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} ChipInfoIdType;
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/*
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* CHIPINFO_PARTNUM_*
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*
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* Definitions of part number/JTAG-ID fields.
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*/
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#define CHIPINFO_PARTNUM_SM_KODIAK 0x192
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#define CHIPINFO_PARTNUM_SC_KODIAK_CHROME 0x193
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#define CHIPINFO_PARTNUM_SC_KODIAK_WINDOWS 0x194
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#define CHIPINFO_PARTNUM_QCM_KODIAK 0x197
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#define CHIPINFO_PARTNUM_QCS_KODIAK 0x198
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#define CHIPINFO_PARTNUM_SMP_KODIAK 0x1A1
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#define CHIPINFO_PARTNUM_SM_KODIAK_LTE_ONLY 0x1B5
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#define CHIPINFO_PARTNUM_SCP_KODIAK 0x1EB
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#define CHIPINFO_PARTNUM_SC_8CGEN3 0x1E3
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#define CHIPINFO_PARTNUM_SCP_8CGEN3 0x20A
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#define CHIPINFO_PARTNUM_KODIAK_SCP_7CGEN3 0x215
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#define CHIPINFO_PARTNUM_QCS_KODIAK_LITE 0x20F
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#define CHIPINFO_PARTNUM_QCM_KODIAK_LITE 0x20E
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#define CHIPINFO_MODEM_SUPPORTED 0x1
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#define CHIPINFO_MODEM_UNKNOWN 0x0
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#define DEVICE_ID 0xFFFF
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struct chipinfo {
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uint32_t chipid;
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uint32_t jtagid;
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bool modem;
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};
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bool socinfo_modem_supported(void);
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@ -0,0 +1,46 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <commonlib/helpers.h>
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#include <device/mmio.h>
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#include <types.h>
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#include <soc/socinfo.h>
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#include <soc/addressmap.h>
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#define JTAG_OFFSET 0xB1014
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static struct chipinfo chipinfolut[] = {
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{ CHIPINFO_ID_SM_KODIAK, CHIPINFO_PARTNUM_SM_KODIAK, CHIPINFO_MODEM_SUPPORTED},
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{ CHIPINFO_ID_SC_KODIAK_CHROME, CHIPINFO_PARTNUM_SC_KODIAK_CHROME,
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CHIPINFO_MODEM_SUPPORTED },
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{ CHIPINFO_ID_SC_KODIAK_WINDOWS, CHIPINFO_PARTNUM_SC_KODIAK_WINDOWS,
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CHIPINFO_MODEM_SUPPORTED},
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{ CHIPINFO_ID_QCM_KODIAK, CHIPINFO_PARTNUM_QCM_KODIAK, CHIPINFO_MODEM_SUPPORTED },
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{ CHIPINFO_ID_QCS_KODIAK, CHIPINFO_PARTNUM_QCS_KODIAK, CHIPINFO_MODEM_UNKNOWN },
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{ CHIPINFO_ID_SMP_KODIAK, CHIPINFO_PARTNUM_SMP_KODIAK, CHIPINFO_MODEM_UNKNOWN },
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{ CHIPINFO_ID_SM_KODIAK_LTE_ONLY, CHIPINFO_PARTNUM_SM_KODIAK_LTE_ONLY,
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CHIPINFO_MODEM_SUPPORTED },
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{ CHIPINFO_ID_SCP_KODIAK, CHIPINFO_PARTNUM_SCP_KODIAK, CHIPINFO_MODEM_UNKNOWN },
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{ CHIPINFO_ID_SC_8CGEN3, CHIPINFO_PARTNUM_SC_8CGEN3, CHIPINFO_MODEM_SUPPORTED },
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{ CHIPINFO_ID_SCP_8CGEN3, CHIPINFO_PARTNUM_SCP_8CGEN3, CHIPINFO_MODEM_UNKNOWN },
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{ CHIPINFO_ID_KODIAK_SCP_7CGEN3, CHIPINFO_PARTNUM_KODIAK_SCP_7CGEN3,
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CHIPINFO_MODEM_UNKNOWN },
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{ CHIPINFO_ID_QCS_KODIAK_LITE, CHIPINFO_PARTNUM_QCS_KODIAK_LITE,
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CHIPINFO_MODEM_UNKNOWN },
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{ CHIPINFO_ID_QCM_KODIAK_LITE, CHIPINFO_PARTNUM_QCM_KODIAK_LITE,
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CHIPINFO_MODEM_UNKNOWN },
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};
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bool socinfo_modem_supported(void)
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{
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uint32_t jtagid;
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int i;
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jtagid = read32((void *)(TLMM_TILE_BASE + JTAG_OFFSET)) & DEVICE_ID;
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for (i = 0; i < ARRAY_SIZE(chipinfolut); i++)
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if (chipinfolut[i].jtagid == jtagid)
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return chipinfolut[i].modem;
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return false;
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}
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