RD890: AMD RD890/SR56X0 CIMX wrapper
Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX chipsets. Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/559 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Kerry Sheh
Marc Jones
parent
e41745e5d6
commit
6b909f21af
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@ -4,6 +4,7 @@ source src/northbridge/amd/gx2/Kconfig
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source src/northbridge/amd/amdfam10/Kconfig
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source src/northbridge/amd/lx/Kconfig
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source src/northbridge/amd/agesa/Kconfig
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source src/northbridge/amd/cimx/Kconfig
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menu "HyperTransport setup"
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#could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8)
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depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
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@ -5,3 +5,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2
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subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx
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subdirs-$(CONFIG_AMD_AGESA) += agesa
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subdirs-$(CONFIG_AMD_NB_CIMX) += cimx
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@ -0,0 +1,24 @@
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#
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# This file is part of the coreboot project.
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#
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#Copyright (C) 2012 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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config AMD_NB_CIMX
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bool
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default n
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source src/northbridge/amd/cimx/rd890/Kconfig
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@ -0,0 +1,20 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890
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@ -0,0 +1,33 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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config NORTHBRIDGE_AMD_CIMX_RD890
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bool
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default n
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select AMD_NB_CIMX
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config REDIRECT_NBCIMX_TRACE_TO_SERIAL
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bool "Redirect AMD Northbridge CIMX Trace to serial console"
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default n
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depends on NORTHBRIDGE_AMD_CIMX_RD890
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help
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This Option allows you to redirect the AMD Northbridge CIMX
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Trace debug information to the serial console.
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Warning: Only enable this option when debuging or tracing AMD CIMX code.
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@ -0,0 +1,25 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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# RD890 Platform Files
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romstage-y += early.c
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ramstage-y += late.c
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@ -0,0 +1,147 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _NB_PLATFORM_H_
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#define _NB_PLATFORM_H_
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#define SERIAL_OUT_SUPPORT //enable serial output
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#define CIMX_DEBUG
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#ifdef CIMX_DEBUG
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#define CIMX_TRACE_SUPPORT
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#define CIMX_ASSERT_SUPPORT
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#endif
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#ifdef CIMX_TRACE_SUPPORT
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#define CIMX_INIT_TRACE(Arguments)
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#if CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL
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#define TRACE_DATA(Ptr, Level) BIOS_DEBUG //always enable
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#define CIMX_TRACE(Argument) do {do_printk Argument;} while (0)
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#else
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#define TRACE_DATA(Ptr, Level)
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#define CIMX_TRACE(Argument)
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#endif
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#else
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#define CIMX_TRACE(Argument)
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#define CIMX_INIT_TRACE(Arguments)
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#endif
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#ifdef CIMX_ASSERT_SUPPORT
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#ifdef ASSERT
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#undef ASSERT
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#define ASSERT CIMX_ASSERT
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#endif
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#ifdef CIMX_TRACE_SUPPORT
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#define CIMX_ASSERT(x) if(!(x)) {\
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LibAmdTraceDebug (CIMX_TRACE_ALL, (CHAR8 *)"ASSERT !!! "__FILE__" - line %d\n", __LINE__); \
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/*__asm {jmp $}; */\
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}
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//#define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args)
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#else
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#define CIMX_ASSERT(x) if(!(x)) {\
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/*__asm {jmp $}; */\
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}
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#endif
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#else
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#define CIMX_ASSERT(x)
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#endif
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/*----------------------------------------------------------------------------------------
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* E X P O R T E D F U N C T I O N S
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*----------------------------------------------------------------------------------------
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*/
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//#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs)
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#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs, Ptr)
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#ifdef B2_IMAGE
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#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) LibNbEventLog(Class, Info, Param1, Param2, Param3, Param4, CfgPtr)
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#else
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#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr)
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#endif
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// CIMX configuration parameters
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//#define CIMX_B2_IMAGE_BASE_ADDRESS 0xFFF40000
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/**
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* PCIEX_BASE_ADDRESS - Define PCIE base address
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*
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* @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
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*/
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#ifdef MOVE_PCIEBAR_TO_F0000000
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#define PCIEX_BASE_ADDRESS 0xF7000000
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#else
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#define PCIEX_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
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#endif
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#define CIMX_S3_SAVE 1
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#include "cbtypes.h"
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#include <console/console.h>
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#include "amd.h" //cimx typedef
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#include <amdlib.h>
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#include "amdAcpiLib.h"
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#include "amdAcpiMadt.h"
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#include "amdAcpiIvrs.h"
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#include "amdSbLib.h"
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#include "nbPcie.h"
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//must put before the nbType.h
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#include "platform_cfg.h" /*platform dependented configuration */
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#include "nbType.h"
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#include "nbLib.h"
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#include "nbDef.h"
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#include "nbInit.h"
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#include "nbHtInit.h"
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#include "nbIommu.h"
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#include "nbEventLog.h"
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#include "nbRegisters.h"
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#include "nbPcieAspm.h"
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#include "nbPcieLinkWidth.h"
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#include "nbPcieHotplug.h"
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#include "nbPciePortRemap.h"
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#include "nbPcieWorkarounds.h"
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#include "nbPcieCplBuffers.h"
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#include "nbPciePllControl.h"
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#include "nbMiscInit.h"
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#include "nbIoApic.h"
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#include "nbPcieSb.h"
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#include "nbRecovery.h"
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#include "nbMaskedMemoryInit.h"
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#define FIX_PTR_ADDR(x, y) x
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#define TRACE_ALWAYS 0xffffffff
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#define AmdNbDispatcher NULL
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#define CIMX_TRACE_ALL 0xFFFFFFFF
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#define CIMX_NBPOR_TRACE 0xFFFFFFFF
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#define CIMX_NBHT_TRACE 0xFFFFFFFF
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#define CIMX_NBPCIE_TRACE 0xFFFFFFFF
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#define CIMX_NB_TRACE 0xFFFFFFFF
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#define CIMX_NBPCIE_MISC 0xFFFFFFFF
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#endif
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@ -0,0 +1,385 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _AMD_H_
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#define _AMD_H_
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#include "cbtypes.h"
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#define VOLATILE volatile
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#define CALLCONV
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#define ROMDATA
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#define CIMXAPI EFIAPI
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//
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//
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// AGESA Types and Definitions
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//
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//
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#ifndef NULL
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#define NULL 0
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#endif
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#define LAST_ENTRY 0xFFFFFFFF
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#define IOCF8 0xCF8
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#define IOCFC 0xCFC
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#define IN
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#define OUT
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#define IMAGE_SIGNATURE 'DMA$'
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typedef UINTN AGESA_STATUS;
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#define AGESA_SUCCESS ((AGESA_STATUS) 0x0)
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#define AGESA_ALERT ((AGESA_STATUS) 0x40000000)
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#define AGESA_WARNING ((AGESA_STATUS) 0x40000001)
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#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003)
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#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001)
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#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002)
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#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003)
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typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
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typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr);
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typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr);
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///This allocation type is used by the AmdCreateStruct entry point
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typedef enum {
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PreMemHeap = 0, ///< Create heap in cache.
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PostMemDram, ///< Create heap in memory.
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ByHost ///< Create heap by Host.
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} ALLOCATION_METHOD;
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/// These width descriptors are used by the library function, and others, to specify the data size
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typedef enum ACCESS_WIDTH {
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AccessWidth8 = 1, ///< Access width is 8 bits.
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AccessWidth16, ///< Access width is 16 bits.
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AccessWidth32, ///< Access width is 32 bits.
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AccessWidth64, ///< Access width is 64 bits.
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AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
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AccessS3SaveWidth16, ///< Save 16 bits data.
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AccessS3SaveWidth32, ///< Save 32 bits data.
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AccessS3SaveWidth64, ///< Save 64 bits data.
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} ACCESS_WIDTH;
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// AGESA Structures
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/// The standard header AMD NB UEFI drivers
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typedef struct _AMD_CONFIG_PARAMS {
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VOID **PeiServices; ///< Pointer to PEI service table
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VOID *StallPpi; ///< Pointer to Stall PPI
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// UINT32 Func;
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VOID *PcieBasePtr; ///< TBD
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CALLOUT_ENTRY CalloutPtr; ///<pointer to local driver callback function
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CALLOUT_ENTRY InterfaceCalloutPtr; ///<pointer to external interface driver callback function
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} AMD_CONFIG_PARAMS;
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/// AGESA Binary module header structure
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typedef struct _AMD_IMAGE_HEADER {
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IN UINT32 Signature; ///< Binary Signature
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IN CHAR8 CreatorID[8]; ///< 8 characters ID
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IN CHAR8 Version[12]; ///< 12 characters version
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IN UINT32 ModuleInfoOffset; ///< Offset of module
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IN UINT32 EntryPointAddress; ///< Entry address
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IN UINT32 ImageBase; ///< Image base
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IN UINT32 RelocTableOffset; ///< Relocate Table offset
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IN UINT32 ImageSize; ///< Size
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IN UINT16 Checksum; ///< Checksum
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IN UINT8 ImageType; ///< Type
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IN UINT8 V_Reserved; ///< Reserved
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} AMD_IMAGE_HEADER;
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/// AGESA Binary module header structure
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typedef struct _AMD_MODULE_HEADER {
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IN UINT32 ModuleHeaderSignature; ///< Module signature
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IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
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IN CHAR8 ModuleVersion[12]; ///< 12 characters version
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IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher
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IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link
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} AMD_MODULE_HEADER;
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/// Extended PCI address format
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typedef struct {
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IN OUT UINT32 Register:12; ///< Register offset
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IN OUT UINT32 Function:3; ///< Function number
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IN OUT UINT32 Device:5; ///< Device number
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IN OUT UINT32 Bus:8; ///< Bus number
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IN OUT UINT32 Segment:4; ///< Segment
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} EXT_PCI_ADDR;
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/// Union type for PCI address
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typedef union _PCI_ADDR {
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IN UINT32 AddressValue; ///< Formal address
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IN EXT_PCI_ADDR Address; ///< Extended address
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} PCI_ADDR;
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#define FUNC_0 0 // bit-placed for PCI address creation
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#define FUNC_1 1
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#define FUNC_2 2
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#define FUNC_3 3
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#define FUNC_4 4
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#define FUNC_5 5
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#define FUNC_6 6
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#define FUNC_7 7
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||||
// SBDFO - Segment Bus Device Function Offset
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// 31:28 Segment (4-bits)
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// 27:20 Bus (8-bits)
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// 19:15 Device (5-bits)
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// 14:12 Function(3-bits)
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// 11:00 Offset (12-bits)
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#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
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(((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
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#define ILLEGAL_SBDFO 0xFFFFFFFF
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/// CPUID data received registers format
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typedef struct _CPUID_DATA {
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IN OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
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IN OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
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IN OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
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||||
IN OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
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} CPUID_DATA;
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#define WARM_RESET 1
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#define COLD_RESET 2
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/// HT frequency for external callbacks
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||||
typedef enum {
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HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
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HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
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HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
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HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
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HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
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HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
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HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
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HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
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HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
|
||||
HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
|
||||
HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
|
||||
HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
|
||||
HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
|
||||
HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
|
||||
HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
|
||||
HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks
|
||||
} HT_FREQUENCIES;
|
||||
|
||||
#ifndef BIT0
|
||||
#define BIT0 0x0000000000000001ull
|
||||
#endif
|
||||
#ifndef BIT1
|
||||
#define BIT1 0x0000000000000002ull
|
||||
#endif
|
||||
#ifndef BIT2
|
||||
#define BIT2 0x0000000000000004ull
|
||||
#endif
|
||||
#ifndef BIT3
|
||||
#define BIT3 0x0000000000000008ull
|
||||
#endif
|
||||
#ifndef BIT4
|
||||
#define BIT4 0x0000000000000010ull
|
||||
#endif
|
||||
#ifndef BIT5
|
||||
#define BIT5 0x0000000000000020ull
|
||||
#endif
|
||||
#ifndef BIT6
|
||||
#define BIT6 0x0000000000000040ull
|
||||
#endif
|
||||
#ifndef BIT7
|
||||
#define BIT7 0x0000000000000080ull
|
||||
#endif
|
||||
#ifndef BIT8
|
||||
#define BIT8 0x0000000000000100ull
|
||||
#endif
|
||||
#ifndef BIT9
|
||||
#define BIT9 0x0000000000000200ull
|
||||
#endif
|
||||
#ifndef BIT10
|
||||
#define BIT10 0x0000000000000400ull
|
||||
#endif
|
||||
#ifndef BIT11
|
||||
#define BIT11 0x0000000000000800ull
|
||||
#endif
|
||||
#ifndef BIT12
|
||||
#define BIT12 0x0000000000001000ull
|
||||
#endif
|
||||
#ifndef BIT13
|
||||
#define BIT13 0x0000000000002000ull
|
||||
#endif
|
||||
#ifndef BIT14
|
||||
#define BIT14 0x0000000000004000ull
|
||||
#endif
|
||||
#ifndef BIT15
|
||||
#define BIT15 0x0000000000008000ull
|
||||
#endif
|
||||
#ifndef BIT16
|
||||
#define BIT16 0x0000000000010000ull
|
||||
#endif
|
||||
#ifndef BIT17
|
||||
#define BIT17 0x0000000000020000ull
|
||||
#endif
|
||||
#ifndef BIT18
|
||||
#define BIT18 0x0000000000040000ull
|
||||
#endif
|
||||
#ifndef BIT19
|
||||
#define BIT19 0x0000000000080000ull
|
||||
#endif
|
||||
#ifndef BIT20
|
||||
#define BIT20 0x0000000000100000ull
|
||||
#endif
|
||||
#ifndef BIT21
|
||||
#define BIT21 0x0000000000200000ull
|
||||
#endif
|
||||
#ifndef BIT22
|
||||
#define BIT22 0x0000000000400000ull
|
||||
#endif
|
||||
#ifndef BIT23
|
||||
#define BIT23 0x0000000000800000ull
|
||||
#endif
|
||||
#ifndef BIT24
|
||||
#define BIT24 0x0000000001000000ull
|
||||
#endif
|
||||
#ifndef BIT25
|
||||
#define BIT25 0x0000000002000000ull
|
||||
#endif
|
||||
#ifndef BIT26
|
||||
#define BIT26 0x0000000004000000ull
|
||||
#endif
|
||||
#ifndef BIT27
|
||||
#define BIT27 0x0000000008000000ull
|
||||
#endif
|
||||
#ifndef BIT28
|
||||
#define BIT28 0x0000000010000000ull
|
||||
#endif
|
||||
#ifndef BIT29
|
||||
#define BIT29 0x0000000020000000ull
|
||||
#endif
|
||||
#ifndef BIT30
|
||||
#define BIT30 0x0000000040000000ull
|
||||
#endif
|
||||
#ifndef BIT31
|
||||
#define BIT31 0x0000000080000000ull
|
||||
#endif
|
||||
#ifndef BIT32
|
||||
#define BIT32 0x0000000100000000ull
|
||||
#endif
|
||||
#ifndef BIT33
|
||||
#define BIT33 0x0000000200000000ull
|
||||
#endif
|
||||
#ifndef BIT34
|
||||
#define BIT34 0x0000000400000000ull
|
||||
#endif
|
||||
#ifndef BIT35
|
||||
#define BIT35 0x0000000800000000ull
|
||||
#endif
|
||||
#ifndef BIT36
|
||||
#define BIT36 0x0000001000000000ull
|
||||
#endif
|
||||
#ifndef BIT37
|
||||
#define BIT37 0x0000002000000000ull
|
||||
#endif
|
||||
#ifndef BIT38
|
||||
#define BIT38 0x0000004000000000ull
|
||||
#endif
|
||||
#ifndef BIT39
|
||||
#define BIT39 0x0000008000000000ull
|
||||
#endif
|
||||
#ifndef BIT40
|
||||
#define BIT40 0x0000010000000000ull
|
||||
#endif
|
||||
#ifndef BIT41
|
||||
#define BIT41 0x0000020000000000ull
|
||||
#endif
|
||||
#ifndef BIT42
|
||||
#define BIT42 0x0000040000000000ull
|
||||
#endif
|
||||
#ifndef BIT43
|
||||
#define BIT43 0x0000080000000000ull
|
||||
#endif
|
||||
#ifndef BIT44
|
||||
#define BIT44 0x0000100000000000ull
|
||||
#endif
|
||||
#ifndef BIT45
|
||||
#define BIT45 0x0000200000000000ull
|
||||
#endif
|
||||
#ifndef BIT46
|
||||
#define BIT46 0x0000400000000000ull
|
||||
#endif
|
||||
#ifndef BIT47
|
||||
#define BIT47 0x0000800000000000ull
|
||||
#endif
|
||||
#ifndef BIT48
|
||||
#define BIT48 0x0001000000000000ull
|
||||
#endif
|
||||
#ifndef BIT49
|
||||
#define BIT49 0x0002000000000000ull
|
||||
#endif
|
||||
#ifndef BIT50
|
||||
#define BIT50 0x0004000000000000ull
|
||||
#endif
|
||||
#ifndef BIT51
|
||||
#define BIT51 0x0008000000000000ull
|
||||
#endif
|
||||
#ifndef BIT52
|
||||
#define BIT52 0x0010000000000000ull
|
||||
#endif
|
||||
#ifndef BIT53
|
||||
#define BIT53 0x0020000000000000ull
|
||||
#endif
|
||||
#ifndef BIT54
|
||||
#define BIT54 0x0040000000000000ull
|
||||
#endif
|
||||
#ifndef BIT55
|
||||
#define BIT55 0x0080000000000000ull
|
||||
#endif
|
||||
#ifndef BIT56
|
||||
#define BIT56 0x0100000000000000ull
|
||||
#endif
|
||||
#ifndef BIT57
|
||||
#define BIT57 0x0200000000000000ull
|
||||
#endif
|
||||
#ifndef BIT58
|
||||
#define BIT58 0x0400000000000000ull
|
||||
#endif
|
||||
#ifndef BIT59
|
||||
#define BIT59 0x0800000000000000ull
|
||||
#endif
|
||||
#ifndef BIT60
|
||||
#define BIT60 0x1000000000000000ull
|
||||
#endif
|
||||
#ifndef BIT61
|
||||
#define BIT61 0x2000000000000000ull
|
||||
#endif
|
||||
#ifndef BIT62
|
||||
#define BIT62 0x4000000000000000ull
|
||||
#endif
|
||||
#ifndef BIT63
|
||||
#define BIT63 0x8000000000000000ull
|
||||
#endif
|
||||
|
||||
#ifdef ASSERT
|
||||
#undef ASSERT
|
||||
#define ASSERT(x)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 - 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _CBTYPES_H_
|
||||
#define _CBTYPES_H_
|
||||
|
||||
//#include <stdint.h>
|
||||
|
||||
/*
|
||||
typedef int64_t __int64;
|
||||
typedef void VOID;
|
||||
typedef uint32_t UINTN;//
|
||||
typedef int8_t CHAR8;
|
||||
typedef uint8_t UINT8;
|
||||
typedef uint16_t UINT16;
|
||||
typedef uint32_t UINT32;
|
||||
typedef uint64_t UINT64;
|
||||
*/
|
||||
typedef signed long long __int64;
|
||||
typedef void VOID;
|
||||
typedef unsigned int UINTN;//
|
||||
typedef signed char CHAR8;
|
||||
typedef unsigned char UINT8;
|
||||
typedef unsigned short UINT16;
|
||||
typedef unsigned int UINT32;
|
||||
typedef signed int INT32;
|
||||
typedef unsigned long long UINT64;
|
||||
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
typedef unsigned char BOOLEAN;
|
||||
|
||||
#ifndef VOLATILE
|
||||
#define VOLATILE volatile
|
||||
#endif
|
||||
|
||||
#ifndef IN
|
||||
#define IN
|
||||
#endif
|
||||
#ifndef OUT
|
||||
#define OUT
|
||||
#endif
|
||||
|
||||
//porting.h
|
||||
#ifndef CONST
|
||||
#define CONST const
|
||||
#endif
|
||||
#ifndef STATIC
|
||||
#define STATIC static
|
||||
#endif
|
||||
#ifndef VOLATILE
|
||||
#define VOLATILE volatile
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CIMX_RD890_CHIP_H_
|
||||
#define _CIMX_RD890_CHIP_H_
|
||||
|
||||
extern struct chip_operations northbridge_amd_cimx_rd890_ops;
|
||||
|
||||
/**
|
||||
* RD890 specific device configuration
|
||||
*/
|
||||
struct northbridge_amd_cimx_rd890_config
|
||||
{
|
||||
u8 gpp1_configuration;
|
||||
u8 gpp2_configuration;
|
||||
u8 gpp3a_configuration;
|
||||
u16 port_enable;
|
||||
};
|
||||
|
||||
#endif /* _CIMX_RD890_CHIP_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "NbPlatform.h"
|
||||
#include "rd890_cfg.h"
|
||||
#include "nb_cimx.h"
|
||||
|
||||
|
||||
/**
|
||||
* @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b
|
||||
*
|
||||
* SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
|
||||
* Disable all Pcie Bridges to work around It.
|
||||
*/
|
||||
void sr56x0_rd890_disable_pcie_bridge(void)
|
||||
{
|
||||
u32 nb_dev;
|
||||
u32 mask;
|
||||
u32 val;
|
||||
AMD_NB_CONFIG_BLOCK cfg_block;
|
||||
AMD_NB_CONFIG_BLOCK *cfg_ptr = &cfg_block;
|
||||
AMD_NB_CONFIG *nb_cfg = &(cfg_block.Northbridges[0]);
|
||||
|
||||
nb_cfg->ConfigPtr = &cfg_ptr;
|
||||
nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
|
||||
val = (1 << 2) | (1 << 3); /*GPP1*/
|
||||
val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/
|
||||
val |= (1 << 18) | (1 << 19); /*GPP2*/
|
||||
val |= (1 << 20); /*GPP3b*/
|
||||
mask = ~val;
|
||||
LibNbPciIndexRMW(nb_dev | NB_MISC_INDEX, NB_MISC_REG0C,
|
||||
AccessS3SaveWidth32,
|
||||
mask,
|
||||
val,
|
||||
nb_cfg);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief South Bridge CIMx romstage entry,
|
||||
* wrapper of AmdPowerOnResetInit entry point.
|
||||
*/
|
||||
void nb_Poweron_Init(void)
|
||||
{
|
||||
NB_CONFIG nb_cfg[MAX_NB_COUNT];
|
||||
HT_CONFIG ht_cfg[MAX_NB_COUNT];
|
||||
PCIE_CONFIG pcie_cfg[MAX_NB_COUNT];
|
||||
AMD_NB_CONFIG_BLOCK gConfig;
|
||||
AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig;
|
||||
AGESA_STATUS status;
|
||||
|
||||
printk(BIOS_DEBUG, "cimx/rd890 early.c %s() Start\n", __func__);
|
||||
CIMX_INIT_TRACE();
|
||||
CIMX_TRACE((BIOS_DEBUG, "NbPowerOnResetInit entry\n"));
|
||||
rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]);
|
||||
|
||||
if (ConfigPtr->StandardHeader.CalloutPtr != NULL) {
|
||||
ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetNbPorConfig, 0, &gConfig);
|
||||
}
|
||||
|
||||
status = AmdPowerOnResetInit(&gConfig);
|
||||
printk(BIOS_DEBUG, "cimx/rd890 early.c %s() End. return status=%x\n", __func__, status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief South Bridge CIMx romstage entry,
|
||||
* wrapper of AmdHtInit entry point.
|
||||
*/
|
||||
void nb_Ht_Init(void)
|
||||
{
|
||||
AGESA_STATUS status;
|
||||
NB_CONFIG nb_cfg[MAX_NB_COUNT];
|
||||
HT_CONFIG ht_cfg[MAX_NB_COUNT];
|
||||
PCIE_CONFIG pcie_cfg[MAX_NB_COUNT];
|
||||
AMD_NB_CONFIG_BLOCK gConfig;
|
||||
AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig;
|
||||
u32 i;
|
||||
|
||||
rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]);
|
||||
|
||||
//Initialize HT structure
|
||||
LibSystemApiCall(AmdHtInitializer, &gConfig);
|
||||
for (i = 0; i < MAX_NB_COUNT; i ++) {
|
||||
if (ConfigPtr->StandardHeader.CalloutPtr != NULL) {
|
||||
ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetHtConfig, 0, (VOID*)&(gConfig.Northbridges[i]));
|
||||
}
|
||||
}
|
||||
|
||||
status = LibSystemApiCall(AmdHtInit, &gConfig);
|
||||
printk(BIOS_DEBUG, "AmdHtInit status: %x\n", status);
|
||||
}
|
||||
|
||||
void nb_S3_Init(void)
|
||||
{
|
||||
//TODO
|
||||
}
|
||||
|
|
@ -0,0 +1,257 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "NbPlatform.h"
|
||||
#include "nb_cimx.h"
|
||||
#include "rd890_cfg.h"
|
||||
|
||||
|
||||
/**
|
||||
* Global RD890 CIMX Configuration structure
|
||||
*/
|
||||
static NB_CONFIG nb_cfg[MAX_NB_COUNT];
|
||||
static HT_CONFIG ht_cfg[MAX_NB_COUNT];
|
||||
static PCIE_CONFIG pcie_cfg[MAX_NB_COUNT];
|
||||
static AMD_NB_CONFIG_BLOCK gConfig;
|
||||
|
||||
|
||||
/**
|
||||
* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree
|
||||
* After this call EP are fully operational on particular NB
|
||||
*/
|
||||
void nb_Pcie_Early_Init(void)
|
||||
{
|
||||
LibSystemApiCall(AmdPcieEarlyInit, &gConfig); //AmdPcieEarlyInit(&gConfig);
|
||||
}
|
||||
|
||||
void nb_Pcie_Late_Init(void)
|
||||
{
|
||||
LibSystemApiCall(AmdPcieLateInit, &gConfig);
|
||||
}
|
||||
|
||||
void nb_Early_Post_Init(void)
|
||||
{
|
||||
LibSystemApiCall(AmdEarlyPostInit, &gConfig);
|
||||
}
|
||||
|
||||
void nb_Mid_Post_Init(void)
|
||||
{
|
||||
LibSystemApiCall(AmdMidPostInit, &gConfig);
|
||||
}
|
||||
|
||||
void nb_Late_Post_Init(void)
|
||||
{
|
||||
LibSystemApiCall(AmdLatePostInit, &gConfig);
|
||||
}
|
||||
|
||||
static void rd890_enable(device_t dev)
|
||||
{
|
||||
u32 address = 0;
|
||||
u32 mask;
|
||||
u32 val;
|
||||
u32 devfn;
|
||||
u32 port;
|
||||
AMD_NB_CONFIG *NbConfigPtr = NULL;
|
||||
|
||||
u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */
|
||||
address = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
|
||||
NbConfigPtr = &(gConfig.Northbridges[nb_index]);
|
||||
|
||||
devfn = dev->path.pci.devfn;
|
||||
port = devfn >> 3;
|
||||
printk(BIOS_INFO, "rd890_enable ");
|
||||
printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n",
|
||||
0, (devfn >> 3), (devfn & 0x07), dev->enabled);
|
||||
if (port != 0) {
|
||||
if (dev->enabled) {
|
||||
NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = OFF;
|
||||
} else {
|
||||
NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = ON;
|
||||
}
|
||||
}
|
||||
|
||||
switch (port) {
|
||||
case 0x0: /* Root Complex, and ClkConfig */
|
||||
|
||||
if ((devfn & 0x07) == 1) { /* skip dev-0 fun-1 */
|
||||
break;
|
||||
}
|
||||
|
||||
/* CIMX configuration defualt initialize */
|
||||
rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]);
|
||||
if (gConfig.StandardHeader.CalloutPtr != NULL) {
|
||||
/* NOTE: not use LibNbCallBack */
|
||||
gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr);
|
||||
}
|
||||
/* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree
|
||||
* After this call EP are fully operational on particular NB
|
||||
*/
|
||||
nb_Pcie_Early_Init();
|
||||
break;
|
||||
|
||||
case 0x2: /* Gpp1 Port0 */
|
||||
case 0x3: /* Gpp1 Port1 */
|
||||
mask = ~(1 << port);
|
||||
val = (dev->enabled ? 0 : 1) << port;
|
||||
LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr);
|
||||
break;
|
||||
|
||||
case 0x4: /* Gpp3a Port0 */
|
||||
case 0x5: /* Gpp3a Port1 */
|
||||
case 0x6: /* Gpp3a Port2 */
|
||||
case 0x7: /* Gpp3a Port3 */
|
||||
mask = ~(1 << port);
|
||||
val = (dev->enabled ? 0 : 1) << port;
|
||||
LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr);
|
||||
break;
|
||||
|
||||
case 0x8: /* SB ALink */
|
||||
mask = ~(1 << 6);
|
||||
val = (dev->enabled ? 1 : 0) << 6;
|
||||
LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr);
|
||||
break;
|
||||
|
||||
case 0x9: /* Gpp3a Port4 */
|
||||
case 0xa: /* Gpp3a Port5 */
|
||||
mask = ~(1 << (7 + port));
|
||||
val = (dev->enabled ? 0 : 1) << (7 + port);
|
||||
LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr);
|
||||
break;
|
||||
|
||||
case 0xb: /* Gpp2 Port0 */
|
||||
case 0xc: /* Gpp2 Port1 */
|
||||
mask = ~(1 << (7 + port));
|
||||
val = (dev->enabled ? 0 : 1) << (7 + port);
|
||||
LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr);
|
||||
break;
|
||||
|
||||
case 0xd: /* Gpp3b */
|
||||
mask = ~(1 << (7 + port));
|
||||
val = (dev->enabled ? 0 : 1) << (7 + port);
|
||||
LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr);
|
||||
|
||||
/* Init NB at Early Post */
|
||||
if (gConfig.StandardHeader.CalloutPtr != NULL) {
|
||||
gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr);
|
||||
}
|
||||
nb_Early_Post_Init();//
|
||||
if (gConfig.StandardHeader.CalloutPtr != NULL) {
|
||||
gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr);
|
||||
}
|
||||
nb_Mid_Post_Init();
|
||||
nb_Pcie_Late_Init();
|
||||
if (gConfig.StandardHeader.CalloutPtr != NULL) {
|
||||
gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr);
|
||||
}
|
||||
nb_Late_Post_Init();
|
||||
break;
|
||||
|
||||
default:
|
||||
printk(BIOS_INFO, "Buggy Device Tree\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
struct chip_operations northbridge_amd_cimx_rd890_ops = {
|
||||
CHIP_NAME("ATI rd890")
|
||||
.enable_dev = rd890_enable,
|
||||
};
|
||||
|
||||
|
||||
static void ioapic_init(struct device *dev)
|
||||
{
|
||||
u32 ioapic_base;
|
||||
|
||||
pci_write_config32(dev, 0xF8, 0x1);
|
||||
ioapic_base = pci_read_config32(dev, 0xFC) & 0xfffffff0;
|
||||
setup_ioapic(ioapic_base, 1);
|
||||
}
|
||||
|
||||
static void rd890_read_resource(struct device *dev)
|
||||
{
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* rpr6.2.(1). Write the Base Address Register (BAR) */
|
||||
pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */
|
||||
pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */
|
||||
|
||||
compact_resources(dev);
|
||||
}
|
||||
|
||||
/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */
|
||||
static void rd890_set_resources(struct device *dev)
|
||||
{
|
||||
pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */
|
||||
pci_dev_set_resources(dev);
|
||||
}
|
||||
|
||||
static struct pci_operations lops_pci = {
|
||||
.set_subsystem = pci_dev_set_subsystem,
|
||||
};
|
||||
|
||||
static struct device_operations ht_ops = {
|
||||
.read_resources = rd890_read_resource,
|
||||
.set_resources = rd890_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = ioapic_init,
|
||||
.scan_bus = 0,
|
||||
.ops_pci = &lops_pci,
|
||||
};
|
||||
|
||||
static const struct pci_driver ht_driver_sr5690 __pci_driver = {
|
||||
.ops = &ht_ops,
|
||||
.vendor = PCI_VENDOR_ID_ATI,
|
||||
.device = PCI_DEVICE_ID_AMD_SR5690_HT,
|
||||
};
|
||||
|
||||
static const struct pci_driver ht_driver_sr5670 __pci_driver = {
|
||||
.ops = &ht_ops,
|
||||
.vendor = PCI_VENDOR_ID_ATI,
|
||||
.device = PCI_DEVICE_ID_AMD_SR5670_HT,
|
||||
};
|
||||
|
||||
static const struct pci_driver ht_driver_sr5650 __pci_driver = {
|
||||
.ops = &ht_ops,
|
||||
.vendor = PCI_VENDOR_ID_ATI,
|
||||
.device = PCI_DEVICE_ID_AMD_SR5650_HT,
|
||||
};
|
||||
|
||||
static const struct pci_driver ht_driver_rd890tv __pci_driver = {
|
||||
.ops = &ht_ops,
|
||||
.vendor = PCI_VENDOR_ID_ATI,
|
||||
.device = PCI_DEVICE_ID_AMD_RD890TV_HT,
|
||||
};
|
||||
|
||||
static const struct pci_driver ht_driver_rd890 __pci_driver = {
|
||||
.ops = &ht_ops,
|
||||
.vendor = PCI_VENDOR_ID_ATI,
|
||||
.device = PCI_DEVICE_ID_AMD_RD890_HT,
|
||||
};
|
||||
|
||||
static const struct pci_driver ht_driver_990fx __pci_driver = {
|
||||
.ops = &ht_ops,
|
||||
.vendor = PCI_VENDOR_ID_ATI,
|
||||
.device = PCI_DEVICE_ID_AMD_990FX_HT,
|
||||
};
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _NB_CIMX_H_
|
||||
#define _NB_CIMX_H_
|
||||
|
||||
/**
|
||||
* @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b
|
||||
*
|
||||
* SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
|
||||
* Disable all Pcie Bridges to work around It.
|
||||
*/
|
||||
void sr56x0_rd890_disable_pcie_bridge(void);
|
||||
|
||||
/**
|
||||
* Northbridge CIMX entries point
|
||||
*/
|
||||
void nb_Poweron_Init(void);
|
||||
void nb_Ht_Init(void);
|
||||
void nb_S3_Init(void);
|
||||
void nb_Early_Post_Init(void);
|
||||
void nb_Mid_Post_Init(void);
|
||||
void nb_Late_Post_Init(void);
|
||||
void nb_Pcie_Early_Init(void);
|
||||
void nb_Pcie_Late_Init(void);
|
||||
|
||||
#endif//_RD890_EARLY_H_
|
||||
|
||||
Loading…
Reference in New Issue