From 6b931125459250a015f6de438dbf9c23e9cd6d75 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 1 Nov 2018 17:48:37 +0100 Subject: [PATCH] sb/intel: Deduplicate vbnv_cmos_failed and rtc_init * Move all implementations to into common folder. * Add rtc.c for rtc based functions Allows all Intel based platforms to use VBOOT_VBNV_CMOS. Change-Id: Ia494e6d418af6f907c648376674776c54d95ba71 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/29427 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- .../intel/bd82x6x/early_pch_common.c | 16 ----- src/southbridge/intel/bd82x6x/lpc.c | 19 +----- src/southbridge/intel/bd82x6x/pch.h | 3 - src/southbridge/intel/common/Makefile.inc | 5 ++ src/southbridge/intel/common/pmutil.h | 3 + src/southbridge/intel/common/rtc.c | 58 +++++++++++++++++++ src/southbridge/intel/common/rtc.h | 24 ++++++++ src/southbridge/intel/lynxpoint/lpc.c | 19 +----- src/southbridge/intel/lynxpoint/pch.h | 3 - src/southbridge/intel/lynxpoint/pmutil.c | 16 ----- 10 files changed, 94 insertions(+), 72 deletions(-) create mode 100644 src/southbridge/intel/common/rtc.c create mode 100644 src/southbridge/intel/common/rtc.h diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c index f1ac4f0e77..3e151fcb75 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_common.c +++ b/src/southbridge/intel/bd82x6x/early_pch_common.c @@ -23,7 +23,6 @@ #include #include #include -#include #if ENV_ROMSTAGE uint64_t get_initial_timestamp(void) @@ -62,18 +61,3 @@ int southbridge_detect_s3_resume(void) return 0; } #endif - -int rtc_failure(void) -{ -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); -#else - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); -#endif - return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD); -} - -int vbnv_cmos_failed(void) -{ - return rtc_failure(); -} diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 271b5b06cc..67f1de6a07 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include @@ -39,6 +38,7 @@ #include #include #include +#include #define NMI_OFF 0 @@ -279,21 +279,6 @@ static void pch_power_options(struct device *dev) RCBA32(0x3f02) = reg32; } -static void pch_rtc_init(struct device *dev) -{ - int rtc_failed = rtc_failure(); - - if (rtc_failed) { - if (IS_ENABLED(CONFIG_ELOG)) - elog_add_event(ELOG_TYPE_RTC_RESET); - pci_update_config8(dev, GEN_PMCON_3, ~RTC_BATTERY_DEAD, 0); - } - - printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - - cmos_init(rtc_failed); -} - /* CougarPoint PCH Power Management init */ static void cpt_pm_init(struct device *dev) { @@ -605,7 +590,7 @@ static void lpc_init(struct device *dev) //gpio_init(dev); /* Initialize the real time clock. */ - pch_rtc_init(dev); + sb_rtc_init(); /* Initialize ISA DMA. */ isa_dma_init(); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index e234ca0036..bb0d5c4a95 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -100,9 +100,6 @@ void early_usb_init (const struct southbridge_usb_port *portmap); #endif - -/* Return non-zero when RTC failure happened. */ -int rtc_failure(void); #endif /* PM I/O Space */ diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 4df559e38d..b87354c5e8 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -54,4 +54,9 @@ smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c +romstage-y += rtc.c +ramstage-y += rtc.c +postcar-y += rtc.c +smm-y += rtc.c + endif diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 26134d9fad..c578982e92 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -21,6 +21,9 @@ #define D31F0_PMBASE 0x40 #define D31F0_GEN_PMCON_3 0xa4 +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) #define D31F0_GPIO_ROUT 0xb8 #define GPI_DISABLE 0x00 #define GPI_IS_SMI 0x01 diff --git a/src/southbridge/intel/common/rtc.c b/src/southbridge/intel/common/rtc.c new file mode 100644 index 0000000000..e9ac2c2deb --- /dev/null +++ b/src/southbridge/intel/common/rtc.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include "pmutil.h" +#include "rtc.h" + +/* PCI Configuration Space (D31:F0): LPC */ +#if defined(__SIMPLE_DEVICE__) +#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) +#else +#define PCH_LPC_DEV dev_find_slot(0, PCI_DEVFN(0x1f, 0)) +#endif + +int rtc_failure(void) +{ + return !!(pci_read_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3) + & RTC_BATTERY_DEAD); +} + +void sb_rtc_init(void) +{ + int rtc_failed = rtc_failure(); + + if (rtc_failed) { + if (IS_ENABLED(CONFIG_ELOG)) + elog_add_event(ELOG_TYPE_RTC_RESET); + pci_update_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3, + ~RTC_BATTERY_DEAD, 0); + } + + printk(BIOS_DEBUG, "RTC: failed = 0x%x\n", rtc_failed); + + cmos_init(rtc_failed); +} + +int vbnv_cmos_failed(void) +{ + return rtc_failure(); +} diff --git a/src/southbridge/intel/common/rtc.h b/src/southbridge/intel/common/rtc.h new file mode 100644 index 0000000000..0d04a51b5e --- /dev/null +++ b/src/southbridge/intel/common/rtc.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_INTEL_RTC_H +#define SOUTHBRIDGE_INTEL_RTC_H + +/* Return non-zero when RTC failure happened. */ +int rtc_failure(void); +void sb_rtc_init(void); + +#endif diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index cf5959ecee..9e0ce8a09e 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include "nvs.h" @@ -37,6 +36,7 @@ #include #include #include +#include #define NMI_OFF 0 @@ -288,21 +288,6 @@ static void pch_power_options(struct device *dev) RCBA16(0x3f02) = reg16; } -static void pch_rtc_init(struct device *dev) -{ - int rtc_failed = rtc_failure(); - - if (rtc_failed) { - if (IS_ENABLED(CONFIG_ELOG)) - elog_add_event(ELOG_TYPE_RTC_RESET); - pci_update_config8(dev, GEN_PMCON_3, ~RTC_BATTERY_DEAD, 0); - } - - printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - - cmos_init(rtc_failed); -} - /* LynxPoint PCH Power Management init */ static void lpt_pm_init(struct device *dev) { @@ -576,7 +561,7 @@ static void lpc_init(struct device *dev) } /* Initialize the real time clock. */ - pch_rtc_init(dev); + sb_rtc_init(); /* Initialize ISA DMA. */ isa_dma_init(); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 1e59479561..5850ab564e 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -172,9 +172,6 @@ void disable_all_gpe(void); void enable_gpe(u32 mask); void disable_gpe(u32 mask); -/* Return non-zero when RTC failure happened. */ -int rtc_failure(void); - #if !defined(__PRE_RAM__) && !defined(__SMM__) #include #include diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index e96d683bb2..b14c1f7c91 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -24,7 +24,6 @@ #include #include #include -#include #include "pch.h" #if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) @@ -554,18 +553,3 @@ void disable_gpe(u32 mask) gpe0_en &= ~mask; outl(gpe0_en, get_pmbase() + gpe0_reg); } - -int rtc_failure(void) -{ -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCI_DEV(0, 31, 0); -#else - struct device *dev = dev_find_slot(0, PCI_DEVFN(31, 0)); -#endif - return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD); -} - -int vbnv_cmos_failed(void) -{ - return rtc_failure(); -}