amd/picasso: Load x86 microcode from CBFS modules
Combine the Ucode binaries for 3 revisions of CPU into one CBFS module. This should be moved to the AMD common code later. BUG=b:153580119 TEST=mandolin Change-Id: Ib08a65b93c045afc97952a809670c85831c0faf7 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -54,6 +54,7 @@ config CPU_SPECIFIC_OPTIONS
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select FSP_USES_CB_STACK
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select UDK_2017_BINDING
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select HAVE_CF9_RESET
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select SUPPORT_CPU_UCODE_IN_CBFS
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config PRERAM_CBMEM_CONSOLE_SIZE
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hex
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@ -64,6 +64,7 @@ ramstage-y += soc_util.c
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ramstage-y += psp.c
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ramstage-y += fsp_params.c
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ramstage-y += config.c
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ramstage-y += update_microcode.c
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all-y += reset.c
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@ -281,9 +282,6 @@ OPT_PSP_PMUD_FILE1=$(call add_opt_prefix, $(PSP_PMUD_FILE1), --subprogram 0 --in
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OPT_PSP_PMUD_FILE2=$(call add_opt_prefix, $(PSP_PMUD_FILE2), --subprogram 0 --instance 4 --pmu-data)
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OPT_PSP_PMUD_FILE3=$(call add_opt_prefix, $(PSP_PMUD_FILE3), --subprogram 1 --instance 1 --pmu-data)
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OPT_PSP_PMUD_FILE4=$(call add_opt_prefix, $(PSP_PMUD_FILE4), --subprogram 1 --instance 4 --pmu-data)
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OPT_PSP_UCODE_FILE1=$(call add_opt_prefix, $(PSP_UCODE_FILE1), --instance 0 --ucode)
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OPT_PSP_UCODE_FILE2=$(call add_opt_prefix, $(PSP_UCODE_FILE2), --instance 1 --ucode)
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OPT_PSP_UCODE_FILE3=$(call add_opt_prefix, $(PSP_UCODE_FILE3), --instance 2 --ucode)
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OPT_MP2CFG_FILE=$(call add_opt_prefix, $(PSP_MP2CFG_FILE), --mp2-config)
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# Copy prebuild APCBs if they exist
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@ -342,9 +340,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \
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$(call strip_quotes, $(PSP_PMUD_FILE2)) \
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$(call strip_quotes, $(PSP_PMUD_FILE3)) \
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$(call strip_quotes, $(PSP_PMUD_FILE4)) \
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$(call strip_quotes, $(PSP_UCODE_FILE1)) \
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$(call strip_quotes, $(PSP_UCODE_FILE2)) \
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$(call strip_quotes, $(PSP_UCODE_FILE3)) \
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$(call strip_quotes, $(PSP_MP2CFG_FILE)) \
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$(call strip_quotes, $(PSP_SMUFW1_SUB1_FILE)) \
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$(call strip_quotes, $(PSP_SMUFW1_SUB2_FILE)) \
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@ -399,9 +394,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \
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$(OPT_PSP_PMUD_FILE2) \
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$(OPT_PSP_PMUD_FILE3) \
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$(OPT_PSP_PMUD_FILE4) \
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$(OPT_PSP_UCODE_FILE1) \
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$(OPT_PSP_UCODE_FILE2) \
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$(OPT_PSP_UCODE_FILE3) \
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$(OPT_MP2CFG_FILE) \
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$(OPT_ABL0_FILE) \
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$(OPT_ABL1_FILE) \
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@ -461,4 +453,6 @@ endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
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$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR)
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cpu_microcode_bins += $(wildcard 3rdparty/amd_blobs/picasso/PSP/UcodePatch_*.bin)
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endif # ($(CONFIG_SOC_AMD_PICASSO),y)
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@ -16,6 +16,7 @@
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#include <soc/smi.h>
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#include <soc/iomap.h>
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#include <console/console.h>
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#include <cpu/amd/microcode.h>
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/*
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* MP and SMM loading initialization.
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@ -108,6 +109,8 @@ static void model_17_init(struct device *dev)
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{
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check_mca();
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setup_lapic();
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amd_update_microcode_from_cbfs();
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}
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static struct device_operations cpu_dev_ops = {
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@ -0,0 +1,91 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stdint.h>
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#include <cpu/amd/microcode.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/msr.h>
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#include <cbfs.h>
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#define MPB_MAX_SIZE 3200
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#define MPB_DATA_OFFSET 32
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struct microcode {
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uint32_t date_code;
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uint32_t patch_id;
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uint16_t mc_patch_data_id;
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uint8_t reserved1[6];
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uint32_t chipset1_dev_id;
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uint32_t chipset2_dev_id;
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uint16_t processor_rev_id;
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uint8_t chipset1_rev_id;
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uint8_t chipset2_rev_id;
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uint8_t reserved2[4];
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uint8_t m_patch_data[MPB_MAX_SIZE-MPB_DATA_OFFSET];
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} __packed;
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static void apply_microcode_patch(const struct microcode *m)
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{
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uint32_t new_patch_id;
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msr_t msr;
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msr.hi = (uint64_t)(uintptr_t)m >> 32;
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msr.lo = (uintptr_t)m & 0xffffffff;
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wrmsr(MSR_PATCH_LOADER, msr);
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printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n",
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m->patch_id);
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msr = rdmsr(MSR_PATCH_LEVEL);
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new_patch_id = msr.lo;
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if (new_patch_id == m->patch_id)
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printk(BIOS_INFO, "microcode: being updated to patch id = 0x%08x succeeded\n",
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new_patch_id);
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else
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printk(BIOS_ERR, "microcode: being updated to patch id = 0x%08x failed\n",
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new_patch_id);
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}
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static uint16_t get_equivalent_processor_rev_id(void)
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{
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uint32_t cpuid_family = cpuid_eax(1);
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return (uint16_t)((cpuid_family & 0xff0000) >> 8 | (cpuid_family & 0xff));
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}
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static void amd_update_microcode(const void *ucode, size_t ucode_len,
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uint16_t equivalent_processor_rev_id)
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{
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const struct microcode *m;
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for (m = (struct microcode *)ucode;
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m < (struct microcode *)ucode + ucode_len/MPB_MAX_SIZE; m++) {
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if (m->processor_rev_id == equivalent_processor_rev_id)
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apply_microcode_patch(m);
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}
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}
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void amd_update_microcode_from_cbfs(void)
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{
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const void *ucode;
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size_t ucode_len;
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uint16_t equivalent_processor_rev_id = get_equivalent_processor_rev_id();
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ucode = cbfs_boot_map_with_leak("cpu_microcode_blob.bin",
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CBFS_TYPE_MICROCODE, &ucode_len);
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if (!ucode) {
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printk(BIOS_WARNING, "cpu_microcode_blob.bin not found. Skipping updates.\n");
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return;
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}
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amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);
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}
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