mb/*/*: Remove AMD agesa family16 boards
These boards use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I43c7075fb6418a86c57c863edccbcb750f8ed402 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans
parent
f9decbb0c7
commit
6baee3d287
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@ -1,168 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <AGESA.h>
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <FchPlatform.h>
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#include "imc.h"
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD, agesa_ReadSpd },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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/**
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* AMD Olivehill Platform ALC272 Verb Table
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*/
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static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = {
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{0x11, 0x411111F0}, // - SPDIF_OUT2
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{0x12, 0x411111F0}, // - DMIC_1/2
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{0x13, 0x411111F0}, // - DMIC_3/4
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{0x14, 0x411111F0}, // Port D - LOUT1
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{0x15, 0x411111F0}, // Port A - LOUT2
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{0x16, 0x411111F0}, //
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{0x17, 0x411111F0}, // Port H - MONO
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{0x18, 0x01a19840}, // Port B - MIC1
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{0x19, 0x411111F0}, // Port F - MIC2
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{0x1a, 0x01813030}, // Port C - LINE1
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{0x1b, 0x411111F0}, // Port E - LINE2
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{0x1d, 0x40130605}, // - PCBEEP
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{0x1e, 0x01441120}, // - SPDIF_OUT1
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{0x21, 0x01214010}, // Port I - HPOUT
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{0xff, 0xffffffff}
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};
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static const CODEC_TBL_LIST OlivehillCodecTableList[] =
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{
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{0x10ec0272, (CODEC_ENTRY*)&Olivehill_Alc272_VerbTbl[0]},
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{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
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};
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#define FAN_INPUT_INTERNAL_DIODE 0
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#define FAN_INPUT_TEMP0 1
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#define FAN_INPUT_TEMP1 2
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#define FAN_INPUT_TEMP2 3
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#define FAN_INPUT_TEMP3 4
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#define FAN_INPUT_TEMP0_FILTER 5
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#define FAN_INPUT_ZERO 6
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#define FAN_INPUT_DISABLED 7
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#define FAN_AUTOMODE (1 << 0)
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#define FAN_LINEARMODE (1 << 1)
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#define FAN_STEPMODE ~(1 << 1)
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#define FAN_POLARITY_HIGH (1 << 2)
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#define FAN_POLARITY_LOW ~(1 << 2)
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/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
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#define FREQ_28KHZ 0x0
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#define FREQ_25KHZ 0x1
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#define FREQ_23KHZ 0x2
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#define FREQ_21KHZ 0x3
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#define FREQ_29KHZ 0x4
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#define FREQ_18KHZ 0x5
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#define FREQ_100HZ 0xF7
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#define FREQ_87HZ 0xF8
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#define FREQ_58HZ 0xF9
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#define FREQ_44HZ 0xFA
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#define FREQ_35HZ 0xFB
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#define FREQ_29HZ 0xFC
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#define FREQ_22HZ 0xFD
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#define FREQ_14HZ 0xFE
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#define FREQ_11HZ 0xFF
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/* Olivehill Hardware Monitor Fan Control
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* Hardware limitation:
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* HWM failed to read the input temperature via I2C,
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* if other software switches the I2C switch by mistake or intention.
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* We recommend using IMC to control Fans, instead of HWM.
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*/
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static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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{
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/* Enable IMC fan control, the recommended way */
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if (CONFIG(HUDSON_IMC_FWM)) {
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imc_reg_init();
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/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
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FchParams->Hwm.HwMonitorEnable = TRUE;
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FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */
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FchParams->Imc.ImcEnable = TRUE;
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FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
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FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
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LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
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/* Thermal Zone Parameter */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;
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/* IMC Fan Policy temperature thresholds */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
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/* IMC Fan Policy PWM Settings */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */
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FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;
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/* NOTE:
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* FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
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* AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it.
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* So we remove it from AGESA code. Please See FchInitLateHwm.
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*/
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} else {
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/* HWM fan control, the way not recommended */
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FchParams->Imc.ImcEnable = FALSE;
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FchParams->Hwm.HwMonitorEnable = TRUE;
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FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */
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}
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}
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void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
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{
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}
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void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
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{
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/* Azalia Controller OEM Codec Table Pointer */
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FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]);
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/* Fan Control */
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oem_fan_control(FchParams_env);
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}
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@ -1,44 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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if BOARD_AMD_OLIVEHILL
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select CPU_AMD_AGESA_FAMILY16_KB
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select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
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select SOUTHBRIDGE_AMD_AGESA_YANGTZE
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select DEFAULT_POST_ON_LPC
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_4096
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select GFXUMA
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config MAINBOARD_DIR
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default "amd/olivehill"
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config MAINBOARD_PART_NUMBER
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default "DB-FT3"
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x200000
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config MAX_CPUS
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int
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default 4
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config IRQ_SLOT_COUNT
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int
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default 11
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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config HUDSON_LEGACY_FREE
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bool
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default y
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endif # BOARD_AMD_OLIVEHILL
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@ -1,2 +0,0 @@
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config BOARD_AMD_OLIVEHILL
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bool "Olive Hill"
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@ -1,11 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += bootblock.c
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romstage-y += buildOpts.c
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romstage-y += BiosCallOuts.c
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romstage-y += OemCustomize.c
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ramstage-y += buildOpts.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += OemCustomize.c
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@ -1,139 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <AGESA.h>
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#include <PlatformMemoryConfiguration.h>
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#include <northbridge/amd/agesa/state_machine.h>
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static const PCIe_PORT_DESCRIPTOR PortList[] = {
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x01, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x02, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x03, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x04, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x05, 0)
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}
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};
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static const PCIe_DDI_DESCRIPTOR DdiList[] = {
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/* DP0 to HDMI0/DP */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
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},
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/* DP1 to FCH */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
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},
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/* DP2 to HDMI1/DP */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3)
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},
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};
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static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.Flags = DESCRIPTOR_TERMINATE_LIST,
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.SocketId = 0,
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.PciePortList = PortList,
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.DdiLinkList = DdiList
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};
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void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
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{
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FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
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FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
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FchReset->Xhci1Enable = FALSE;
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}
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void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
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{
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InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
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}
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/*----------------------------------------------------------------------------------------
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* CUSTOMER OVERRIDES MEMORY TABLE
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*----------------------------------------------------------------------------------------
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*/
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/*
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* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
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* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
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* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
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* use its default conservative settings.
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*/
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static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
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#define SEED_A 0x12
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HW_RXEN_SEED(
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ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
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SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
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SEED_A),
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NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
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NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
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MOTHER_BOARD_LAYERS(LAYERS_4),
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MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
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CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
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ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
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CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
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PSO_END
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};
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void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
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{
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InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
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}
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void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
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{
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/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
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InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
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}
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|
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@ -1,38 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/**
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* @file
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*
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* IDS Option File
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*
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* This file is used to switch on/off IDS features.
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*
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*/
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#ifndef _OPTION_IDS_H_
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#define _OPTION_IDS_H_
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/**
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*
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* This file generates the defaults tables for the Integrated Debug Support
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* Module. The documented build options are imported from a user controlled
|
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* file for processing. The build options for the Integrated Debug Support
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* Module are listed below:
|
||||
*
|
||||
* IDSOPT_IDS_ENABLED
|
||||
* IDSOPT_ERROR_TRAP_ENABLED
|
||||
* IDSOPT_CONTROL_ENABLED
|
||||
* IDSOPT_TRACING_ENABLED
|
||||
* IDSOPT_PERF_ANALYSIS
|
||||
* IDSOPT_ASSERT_ENABLED
|
||||
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
|
||||
*
|
||||
**/
|
||||
|
||||
#define IDSOPT_IDS_ENABLED TRUE
|
||||
//#define IDSOPT_CONTROL_ENABLED TRUE
|
||||
//#define IDSOPT_TRACING_ENABLED TRUE
|
||||
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
|
||||
//#define IDSOPT_PERF_ANALYSIS TRUE
|
||||
#define IDSOPT_ASSERT_ENABLED TRUE
|
||||
|
||||
#endif
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Scope(\_GPE) { /* Start Scope GPE */
|
||||
|
||||
/* General event 3 */
|
||||
Method(_L03) {
|
||||
/* DBGO("\\_GPE\\_L00\n") */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Legacy PM event */
|
||||
Method(_L08) {
|
||||
/* DBGO("\\_GPE\\_L08\n") */
|
||||
}
|
||||
|
||||
/* Temp warning (TWarn) event */
|
||||
Method(_L09) {
|
||||
/* DBGO("\\_GPE\\_L09\n") */
|
||||
/* Notify (\_TZ.TZ00, 0x80) */
|
||||
}
|
||||
|
||||
/* USB controller PME# */
|
||||
Method(_L0B) {
|
||||
/* DBGO("\\_GPE\\_L0B\n") */
|
||||
Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* ExtEvent0 SCI event */
|
||||
Method(_L10) {
|
||||
/* DBGO("\\_GPE\\_L10\n") */
|
||||
}
|
||||
|
||||
/* ExtEvent1 SCI event */
|
||||
Method(_L11) {
|
||||
/* DBGO("\\_GPE\\_L11\n") */
|
||||
}
|
||||
|
||||
/* GPIO0 or GEvent8 event */
|
||||
Method(_L18) {
|
||||
/* DBGO("\\_GPE\\_L18\n") */
|
||||
Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Azalia SCI event */
|
||||
Method(_L1B) {
|
||||
/* DBGO("\\_GPE\\_L1B\n") */
|
||||
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
} /* End Scope GPE */
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
|
||||
/* AcpiGpe0Blk */
|
||||
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
|
||||
Field(GP0B, ByteAcc, NoLock, Preserve) {
|
||||
, 11,
|
||||
USBS, 1,
|
||||
}
|
||||
|
|
@ -1,169 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - F16 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
|
||||
/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
|
||||
Package(){0x0001FFFF, 0, INTB, 0 },
|
||||
Package(){0x0001FFFF, 1, INTC, 0 },
|
||||
|
||||
/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
|
||||
/* FCH devices */
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
|
||||
/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
|
||||
/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
|
||||
Package(){0x0012FFFF, 0, INTC, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0013FFFF, 0, INTC, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0016FFFF, 0, INTC, 0 },
|
||||
Package(){0x0016FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
|
||||
Package(){0x0010FFFF, 0, INTC, 0 },
|
||||
Package(){0x0010FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 17 - SATA controller */
|
||||
Package(){0x0011FFFF, 0, INTD, 0 },
|
||||
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - F15 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
|
||||
Package(){0x0001FFFF, 0, 0, 44 },
|
||||
Package(){0x0001FFFF, 1, 0, 45 },
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridges */
|
||||
Package(){0x0002FFFF, 0, 0, 24 },
|
||||
Package(){0x0002FFFF, 1, 0, 25 },
|
||||
Package(){0x0002FFFF, 2, 0, 26 },
|
||||
Package(){0x0002FFFF, 3, 0, 27 },
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
|
||||
/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
|
||||
Package(){0x0012FFFF, 0, 0, 18 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 17 },
|
||||
|
||||
Package(){0x0016FFFF, 0, 0, 18 },
|
||||
Package(){0x0016FFFF, 1, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
|
||||
Package(){0x0010FFFF, 0, 0, 0x12},
|
||||
Package(){0x0010FFFF, 1, 0, 0x11},
|
||||
|
||||
/* Bus 0, Dev 17 - SATA controller */
|
||||
Package(){0x0011FFFF, 0, 0, 19 },
|
||||
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS2, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
/* GFX */
|
||||
Name(PS4, Package(){
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 24 },
|
||||
Package(){0x0000FFFF, 1, 0, 25 },
|
||||
Package(){0x0000FFFF, 2, 0, 26 },
|
||||
Package(){0x0000FFFF, 3, 0, 27 },
|
||||
})
|
||||
|
||||
/* GPP 0 */
|
||||
Name(PS5, Package(){
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APS5, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 28 },
|
||||
Package(){0x0000FFFF, 1, 0, 29 },
|
||||
Package(){0x0000FFFF, 2, 0, 30 },
|
||||
Package(){0x0000FFFF, 3, 0, 31 },
|
||||
})
|
||||
|
||||
/* GPP 1 */
|
||||
Name(PS6, Package(){
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS6, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 32 },
|
||||
Package(){0x0000FFFF, 1, 0, 33 },
|
||||
Package(){0x0000FFFF, 2, 0, 34 },
|
||||
Package(){0x0000FFFF, 3, 0, 35 },
|
||||
})
|
||||
|
||||
/* GPP 2 */
|
||||
Name(PS7, Package(){
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APS7, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 36 },
|
||||
Package(){0x0000FFFF, 1, 0, 37 },
|
||||
Package(){0x0000FFFF, 2, 0, 38 },
|
||||
Package(){0x0000FFFF, 3, 0, 39 },
|
||||
})
|
||||
|
||||
/* GPP 3 */
|
||||
Name(PS8, Package(){
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS8, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 40 },
|
||||
Package(){0x0000FFFF, 1, 0, 41 },
|
||||
Package(){0x0000FFFF, 2, 0, 42 },
|
||||
Package(){0x0000FFFF, 3, 0, 43 },
|
||||
})
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* No SATA functionality */
|
||||
|
|
@ -1,64 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Wake status package */
|
||||
Name(WKST,Package(){Zero, Zero})
|
||||
|
||||
/*
|
||||
* \_PTS - Prepare to Sleep method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2, etc
|
||||
*
|
||||
* Exit:
|
||||
* -none-
|
||||
*
|
||||
* The _PTS control method is executed at the beginning of the sleep process
|
||||
* for S1-S5. The sleeping value is passed to the _PTS control method. This
|
||||
* control method may be executed a relatively long time before entering the
|
||||
* sleep state and the OS may abort the operation without notification to
|
||||
* the ACPI driver. This method cannot modify the configuration or power
|
||||
* state of any device in the system.
|
||||
*/
|
||||
|
||||
External(\_SB.APTS, MethodObj)
|
||||
External(\_SB.AWAK, MethodObj)
|
||||
|
||||
Method(_PTS, 1) {
|
||||
/* DBGO("\\_PTS\n") */
|
||||
/* DBGO("From S0 to S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO("\n") */
|
||||
|
||||
/* Clear wake status structure. */
|
||||
WKST [0] = 0
|
||||
WKST [1] = 0
|
||||
UPWS = 7
|
||||
\_SB.APTS(Arg0)
|
||||
} /* End Method(\_PTS) */
|
||||
|
||||
/*
|
||||
* \_WAK System Wake method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2
|
||||
*
|
||||
* Exit:
|
||||
* Return package of 2 DWords
|
||||
* Dword 1 - Status
|
||||
* 0x00000000 wake succeeded
|
||||
* 0x00000001 Wake was signaled but failed due to lack of power
|
||||
* 0x00000002 Wake was signaled but failed due to thermal condition
|
||||
* Dword 2 - Power Supply state
|
||||
* if non-zero the effective S-state the power supply entered
|
||||
*/
|
||||
Method(\_WAK, 1) {
|
||||
/* DBGO("\\_WAK\n") */
|
||||
/* DBGO("From S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO(" to S0\n") */
|
||||
USBS = 1
|
||||
|
||||
\_SB.AWAK(Arg0)
|
||||
|
||||
Return(WKST)
|
||||
} /* End Method(\_WAK) */
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
/* SPDX-License-Identifier: CC-PDDC */
|
||||
|
||||
/* Please update the license if adding licensable material. */
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
/* SPDX-License-Identifier: CC-PDDC */
|
||||
|
||||
/* Please update the license if adding licensable material. */
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* USB overcurrent mapping pins. */
|
||||
Name(UOM0, 0)
|
||||
Name(UOM1, 2)
|
||||
Name(UOM2, 0)
|
||||
Name(UOM3, 7)
|
||||
Name(UOM4, 2)
|
||||
Name(UOM5, 2)
|
||||
Name(UOM6, 6)
|
||||
Name(UOM7, 2)
|
||||
Name(UOM8, 6)
|
||||
Name(UOM9, 6)
|
||||
|
|
@ -1 +0,0 @@
|
|||
Category: eval
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <amdblocks/acpimmio.h>
|
||||
#include <arch/io.h>
|
||||
#include <bootblock_common.h>
|
||||
|
||||
void bootblock_mainboard_early_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
|
||||
pm_write8(0xea, 0x1);
|
||||
|
||||
/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
|
||||
for (i = 0; i < 200000; i++)
|
||||
inb(0xcd6);
|
||||
}
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <AGESA.h>
|
||||
|
||||
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
|
||||
#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
|
||||
|
||||
//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
|
||||
//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
|
||||
//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_SRAT FALSE
|
||||
#define BLDOPT_REMOVE_WHEA FALSE
|
||||
#define BLDOPT_REMOVE_CRAT TRUE
|
||||
#define BLDOPT_REMOVE_CDIT TRUE
|
||||
|
||||
/* Build configuration values here. */
|
||||
#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0
|
||||
|
||||
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
|
||||
|
||||
#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
|
||||
#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
|
||||
#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
|
||||
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
|
||||
#define BLDCFG_ENABLE_ECC_FEATURE TRUE
|
||||
#define BLDCFG_ECC_SYNC_FLOOD TRUE
|
||||
|
||||
#define BLDCFG_IOMMU_SUPPORT FALSE
|
||||
|
||||
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
|
||||
|
||||
/* Include the files that instantiate the configuration definitions. */
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuFamRegisters.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "AdvancedApi.h"
|
||||
#include "heapManager.h"
|
||||
#include "CreateStruct.h"
|
||||
#include "cpuFeatures.h"
|
||||
#include "Table.h"
|
||||
#include "cpuEarlyInit.h"
|
||||
#include "cpuLateInit.h"
|
||||
#include "GnbInterface.h"
|
||||
|
||||
#include <PlatformInstall.h>
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
#*****************************************************************************
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#*****************************************************************************
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
444 1 e 1 nmi
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
|
@ -1,52 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip northbridge/amd/agesa/family16kb/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/agesa/family16kb
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x1410 inherit
|
||||
chip northbridge/amd/agesa/family16kb
|
||||
device pci 0.0 on end # Root Complex
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
|
||||
device pci 1.1 on end # Internal Multimedia
|
||||
device pci 2.0 on end # PCIe Host Bridge
|
||||
device pci 2.1 on end # x4 PCIe slot
|
||||
device pci 2.2 on end # mPCIe slot
|
||||
device pci 2.3 on end # Realtek NIC
|
||||
device pci 2.4 on end # Edge Connector
|
||||
device pci 2.5 on end # Edge Connector
|
||||
end #chip northbridge/amd/agesa/family16kb
|
||||
|
||||
chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
|
||||
device pci 10.0 on end # XHCI HC0
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on end # SM
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on end # LPC 0x439d
|
||||
device pci 14.7 on end # SD
|
||||
end #chip southbridge/amd/agesa/hudson
|
||||
|
||||
chip northbridge/amd/agesa/family16kb
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 18.5 on end
|
||||
register "spdAddrLookup" = "
|
||||
{
|
||||
{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
|
||||
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
|
||||
}"
|
||||
end
|
||||
|
||||
end #domain
|
||||
end #northbridge/amd/agesa/family16kb/root_complex
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* DefinitionBlock Statement */
|
||||
#include <acpi/acpi.h>
|
||||
DefinitionBlock (
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x00010001 /* OEM Revision */
|
||||
)
|
||||
{ /* Start of ASL file */
|
||||
#include <acpi/dsdt_top.asl>
|
||||
|
||||
/* Globals for the platform */
|
||||
#include "acpi/mainboard.asl"
|
||||
|
||||
/* Describe the USB Overcurrent pins */
|
||||
#include "acpi/usb_oc.asl"
|
||||
|
||||
/* PCI IRQ mapping for the Southbridge */
|
||||
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
|
||||
|
||||
/* Describe the processor tree (\_SB) */
|
||||
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
|
||||
|
||||
/* Contains the supported sleep states for this chipset */
|
||||
#include <southbridge/amd/common/acpi/sleepstates.asl>
|
||||
|
||||
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
|
||||
#include "acpi/sleep.asl"
|
||||
|
||||
/* System Bus */
|
||||
Scope(\_SB) { /* Start \_SB scope */
|
||||
/* global utility methods expected within the \_SB scope */
|
||||
#include <arch/x86/acpi/globutil.asl>
|
||||
|
||||
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
|
||||
#include "acpi/routing.asl"
|
||||
|
||||
Device(PWRB) {
|
||||
Name(_HID, EISAID("PNP0C0C"))
|
||||
Name(_UID, 0xAA)
|
||||
Name(_PRW, Package () {3, 0x04})
|
||||
Name(_STA, 0x0B)
|
||||
}
|
||||
|
||||
Device(PCI0) {
|
||||
/* Describe the AMD Northbridge */
|
||||
#include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>
|
||||
|
||||
/* Describe the AMD Fusion Controller Hub Southbridge */
|
||||
#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
|
||||
}
|
||||
|
||||
/* Describe PCI INT[A-H] for the Southbridge */
|
||||
#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
|
||||
|
||||
} /* End \_SB scope */
|
||||
|
||||
/* Describe SMBUS for the Southbridge */
|
||||
#include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
|
||||
|
||||
/* Define the General Purpose Events for the platform */
|
||||
#include "acpi/gpe.asl"
|
||||
|
||||
/* Define the Thermal zones and methods for the platform */
|
||||
#include "acpi/thermal.asl"
|
||||
}
|
||||
/* End of ASL file */
|
||||
|
|
@ -1,86 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <commonlib/bsd/helpers.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr = ALIGN_UP(addr, 16);
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *)(addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = 0;
|
||||
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1002;
|
||||
pirq->rtr_device = 0x4384;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* PCI bridge */
|
||||
write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++;
|
||||
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum)
|
||||
pirq->checksum = sum;
|
||||
|
||||
printk(BIOS_INFO, "%s done.\n", __func__);
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/device.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
|
||||
static const u8 mainboard_picr_data[0x54] = {
|
||||
0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x03, 0x04, 0x05, 0x07
|
||||
};
|
||||
static const u8 mainboard_intr_data[0x54] = {
|
||||
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x10, 0x11, 0x12, 0x13
|
||||
};
|
||||
|
||||
/* PIRQ Setup */
|
||||
static void pirq_setup(void)
|
||||
{
|
||||
intr_data_ptr = mainboard_intr_data;
|
||||
picr_data_ptr = mainboard_picr_data;
|
||||
}
|
||||
|
||||
/**********************************************
|
||||
* enable the dedicated function in mainboard.
|
||||
**********************************************/
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
pirq_setup();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -1,103 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia.h>
|
||||
#include <AGESA.h>
|
||||
#include <northbridge/amd/agesa/BiosCallOuts.h>
|
||||
#include <northbridge/amd/agesa/state_machine.h>
|
||||
#include <FchPlatform.h>
|
||||
|
||||
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
|
||||
{
|
||||
{AGESA_DO_RESET, agesa_Reset },
|
||||
{AGESA_READ_SPD, agesa_ReadSpd },
|
||||
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
|
||||
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
|
||||
{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
|
||||
{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
|
||||
{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
|
||||
{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
|
||||
};
|
||||
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
|
||||
|
||||
/**
|
||||
* CODEC Initialization Table for Azalia HD Audio using Realtek ALC662 chip
|
||||
*/
|
||||
static const CODEC_ENTRY Alc662_VerbTbl[] =
|
||||
{
|
||||
{ 0x14, /*01014010*/ /* Port D - green headphone jack */
|
||||
(AZALIA_PINCFG_PORT_JACK << 30)
|
||||
| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
|
||||
| (AZALIA_PINCFG_DEVICE_LINEOUT << 20)
|
||||
| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
|
||||
| (AZALIA_PINCFG_COLOR_GREEN << 12)
|
||||
| (1 << 4)
|
||||
| (0 << 0)
|
||||
},
|
||||
{ 0x15, /*0x90170120*/ /* Port A - white speaker header */
|
||||
(AZALIA_PINCFG_PORT_FIXED << 30)
|
||||
| (AZALIA_PINCFG_LOCATION_INTERNAL << 24)
|
||||
| (AZALIA_PINCFG_DEVICE_SPEAKER << 20)
|
||||
| (AZALIA_PINCFG_CONN_OTHER_ANALOG << 16)
|
||||
| (AZALIA_PINCFG_COLOR_WHITE << 12)
|
||||
| (AZALIA_PINCFG_MISC_IGNORE_PRESENCE << 8)
|
||||
| (2 << 4)
|
||||
| (0 << 0)
|
||||
},
|
||||
{ 0x16, 0x411111F0 }, /* Port G - not connected */
|
||||
{ 0x18, /*0x01A19040*/ /* Port B - pink headphone jack */
|
||||
(AZALIA_PINCFG_PORT_JACK << 30)
|
||||
| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
|
||||
| (AZALIA_PINCFG_DEVICE_MICROPHONE << 20)
|
||||
| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
|
||||
| (AZALIA_PINCFG_COLOR_PINK << 12)
|
||||
| (4 << 4)
|
||||
| (0 << 0)
|
||||
},
|
||||
{ 0x19, /*0x02A19050*/ /* Port F - front panel header mic */
|
||||
(AZALIA_PINCFG_PORT_NC << 30)
|
||||
| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24)
|
||||
| (AZALIA_PINCFG_DEVICE_MICROPHONE << 20)
|
||||
| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
|
||||
| (AZALIA_PINCFG_COLOR_PINK << 12)
|
||||
| (5 << 4)
|
||||
| (0 << 0)
|
||||
},
|
||||
{ 0x1A, /*0x0181304F*/ /* Port C - NL blue headphone jack */
|
||||
(AZALIA_PINCFG_PORT_NC << 30)
|
||||
| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
|
||||
| (AZALIA_PINCFG_DEVICE_LINEIN << 20)
|
||||
| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
|
||||
| (AZALIA_PINCFG_COLOR_BLUE << 12)
|
||||
| (4 << 4)
|
||||
| (0xF << 0)
|
||||
},
|
||||
{ 0x1B, /*0x02214030*/ /* Port E - front panel line-out */
|
||||
(AZALIA_PINCFG_PORT_NC << 30)
|
||||
| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24)
|
||||
| (AZALIA_PINCFG_DEVICE_HP_OUT << 20)
|
||||
| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
|
||||
| (AZALIA_PINCFG_COLOR_GREEN << 12)
|
||||
| (3 << 4)
|
||||
| (0 << 0)
|
||||
},
|
||||
{ 0x1C, 0x411111F0 }, /* CD-in - Not Connected */
|
||||
{ 0x1D, 0x411111F0 }, /* PC Beep - Not Connected */
|
||||
{ 0x1E, 0x411111F0 }, /* S/PDIF - Not connected */
|
||||
{ 0xFF, 0xFFFFFFFF },
|
||||
};
|
||||
|
||||
static const CODEC_TBL_LIST CodecTableList[] =
|
||||
{
|
||||
{0x10ec0662, (CODEC_ENTRY*)Alc662_VerbTbl},
|
||||
{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
|
||||
};
|
||||
|
||||
void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
|
||||
{
|
||||
}
|
||||
|
||||
void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
|
||||
{
|
||||
/* Azalia Controller OEM Codec Table Pointer */
|
||||
FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST*)CodecTableList;
|
||||
}
|
||||
|
|
@ -1,53 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
if BOARD_ASROCK_IMB_A180
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select CPU_AMD_AGESA_FAMILY16_KB
|
||||
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
|
||||
select SOUTHBRIDGE_AMD_AGESA_YANGTZE
|
||||
select DEFAULT_POST_ON_LPC
|
||||
select SUPERIO_WINBOND_W83627UHG
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_4096
|
||||
select GFXUMA
|
||||
|
||||
config MAINBOARD_DIR
|
||||
default "asrock/imb-a180"
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
default "IMB-A180"
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
default 0x200000
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
||||
config ONBOARD_VGA_IS_PRIMARY
|
||||
bool
|
||||
default y
|
||||
|
||||
config HUDSON_LEGACY_FREE
|
||||
bool
|
||||
default y
|
||||
|
||||
# bit 1,0 - pin 0
|
||||
# bit 3,2 - pin 1
|
||||
# bit 5,4 - pin 2
|
||||
# bit 7,6 - pin 3
|
||||
config AZ_PIN
|
||||
hex
|
||||
default 0x2
|
||||
|
||||
endif # BOARD_ASROCK_IMB_A180
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config BOARD_ASROCK_IMB_A180
|
||||
bool "IMB-A180"
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
bootblock-y += bootblock.c
|
||||
|
||||
romstage-y += buildOpts.c
|
||||
romstage-y += BiosCallOuts.c
|
||||
romstage-y += OemCustomize.c
|
||||
|
||||
ramstage-y += buildOpts.c
|
||||
ramstage-y += BiosCallOuts.c
|
||||
ramstage-y += OemCustomize.c
|
||||
|
|
@ -1,140 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <AGESA.h>
|
||||
#include <PlatformMemoryConfiguration.h>
|
||||
|
||||
#include <northbridge/amd/agesa/state_machine.h>
|
||||
|
||||
static const PCIe_PORT_DESCRIPTOR PortList[] = {
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x01, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x02, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x03, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x04, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x05, 0)
|
||||
}
|
||||
};
|
||||
|
||||
static const PCIe_DDI_DESCRIPTOR DdiList[] = {
|
||||
/* DP0 to HDMI0/DP */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
|
||||
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
|
||||
},
|
||||
/* DP1 to FCH */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
|
||||
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
|
||||
},
|
||||
/* DP2 to HDMI1/DP */
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
|
||||
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3)
|
||||
},
|
||||
};
|
||||
|
||||
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
|
||||
.Flags = DESCRIPTOR_TERMINATE_LIST,
|
||||
.SocketId = 0,
|
||||
.PciePortList = PortList,
|
||||
.DdiLinkList = DdiList
|
||||
};
|
||||
|
||||
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
|
||||
{
|
||||
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
|
||||
FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
|
||||
FchReset->Xhci1Enable = FALSE;
|
||||
}
|
||||
|
||||
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
|
||||
{
|
||||
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* CUSTOMER OVERRIDES MEMORY TABLE
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
|
||||
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
|
||||
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
|
||||
* use its default conservative settings.
|
||||
*/
|
||||
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
|
||||
|
||||
#define SEED_A 0x12
|
||||
HW_RXEN_SEED(
|
||||
ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
|
||||
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
|
||||
SEED_A),
|
||||
|
||||
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
|
||||
NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
|
||||
MOTHER_BOARD_LAYERS(LAYERS_4),
|
||||
|
||||
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
|
||||
CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
|
||||
ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
|
||||
CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
|
||||
|
||||
PSO_END
|
||||
};
|
||||
|
||||
void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
|
||||
{
|
||||
InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
|
||||
}
|
||||
|
||||
void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
|
||||
{
|
||||
/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
|
||||
InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
|
||||
}
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* IDS Option File
|
||||
*
|
||||
* This file is used to switch on/off IDS features.
|
||||
*
|
||||
*/
|
||||
#ifndef _OPTION_IDS_H_
|
||||
#define _OPTION_IDS_H_
|
||||
|
||||
/**
|
||||
*
|
||||
* This file generates the defaults tables for the Integrated Debug Support
|
||||
* Module. The documented build options are imported from a user controlled
|
||||
* file for processing. The build options for the Integrated Debug Support
|
||||
* Module are listed below:
|
||||
*
|
||||
* IDSOPT_IDS_ENABLED
|
||||
* IDSOPT_ERROR_TRAP_ENABLED
|
||||
* IDSOPT_CONTROL_ENABLED
|
||||
* IDSOPT_TRACING_ENABLED
|
||||
* IDSOPT_PERF_ANALYSIS
|
||||
* IDSOPT_ASSERT_ENABLED
|
||||
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
|
||||
*
|
||||
**/
|
||||
|
||||
#define IDSOPT_IDS_ENABLED TRUE
|
||||
//#define IDSOPT_CONTROL_ENABLED TRUE
|
||||
//#define IDSOPT_TRACING_ENABLED TRUE
|
||||
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
|
||||
//#define IDSOPT_PERF_ANALYSIS TRUE
|
||||
#define IDSOPT_ASSERT_ENABLED TRUE
|
||||
|
||||
#endif
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Scope(\_GPE) { /* Start Scope GPE */
|
||||
|
||||
/* General event 3 */
|
||||
Method(_L03) {
|
||||
/* DBGO("\\_GPE\\_L00\n") */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Legacy PM event */
|
||||
Method(_L08) {
|
||||
/* DBGO("\\_GPE\\_L08\n") */
|
||||
}
|
||||
|
||||
/* Temp warning (TWarn) event */
|
||||
Method(_L09) {
|
||||
/* DBGO("\\_GPE\\_L09\n") */
|
||||
/* Notify (\_TZ.TZ00, 0x80) */
|
||||
}
|
||||
|
||||
/* USB controller PME# */
|
||||
Method(_L0B) {
|
||||
/* DBGO("\\_GPE\\_L0B\n") */
|
||||
Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* ExtEvent0 SCI event */
|
||||
Method(_L10) {
|
||||
/* DBGO("\\_GPE\\_L10\n") */
|
||||
}
|
||||
|
||||
/* ExtEvent1 SCI event */
|
||||
Method(_L11) {
|
||||
/* DBGO("\\_GPE\\_L11\n") */
|
||||
}
|
||||
|
||||
/* GPIO0 or GEvent8 event */
|
||||
Method(_L18) {
|
||||
/* DBGO("\\_GPE\\_L18\n") */
|
||||
Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Azalia SCI event */
|
||||
Method(_L1B) {
|
||||
/* DBGO("\\_GPE\\_L1B\n") */
|
||||
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
} /* End Scope GPE */
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
|
||||
/* AcpiGpe0Blk */
|
||||
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
|
||||
Field(GP0B, ByteAcc, NoLock, Preserve) {
|
||||
, 11,
|
||||
USBS, 1,
|
||||
}
|
||||
|
|
@ -1,171 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - F16 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
|
||||
/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
|
||||
Package(){0x0001FFFF, 0, INTB, 0 },
|
||||
Package(){0x0001FFFF, 1, INTC, 0 },
|
||||
|
||||
|
||||
/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
|
||||
/* FCH devices */
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
|
||||
/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
|
||||
/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
|
||||
Package(){0x0012FFFF, 0, INTC, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0013FFFF, 0, INTC, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0016FFFF, 0, INTC, 0 },
|
||||
Package(){0x0016FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
|
||||
Package(){0x0010FFFF, 0, INTC, 0 },
|
||||
Package(){0x0010FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 17 - SATA controller */
|
||||
Package(){0x0011FFFF, 0, INTD, 0 },
|
||||
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - F15 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
|
||||
Package(){0x0001FFFF, 0, 0, 44 },
|
||||
Package(){0x0001FFFF, 1, 0, 45 },
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridges */
|
||||
Package(){0x0002FFFF, 0, 0, 24 },
|
||||
Package(){0x0002FFFF, 1, 0, 25 },
|
||||
Package(){0x0002FFFF, 2, 0, 26 },
|
||||
Package(){0x0002FFFF, 3, 0, 27 },
|
||||
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
|
||||
/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
|
||||
Package(){0x0012FFFF, 0, 0, 18 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 17 },
|
||||
|
||||
Package(){0x0016FFFF, 0, 0, 18 },
|
||||
Package(){0x0016FFFF, 1, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
|
||||
Package(){0x0010FFFF, 0, 0, 0x12},
|
||||
Package(){0x0010FFFF, 1, 0, 0x11},
|
||||
|
||||
/* Bus 0, Dev 17 - SATA controller */
|
||||
Package(){0x0011FFFF, 0, 0, 19 },
|
||||
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS2, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
/* GFX */
|
||||
Name(PS4, Package(){
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 24 },
|
||||
Package(){0x0000FFFF, 1, 0, 25 },
|
||||
Package(){0x0000FFFF, 2, 0, 26 },
|
||||
Package(){0x0000FFFF, 3, 0, 27 },
|
||||
})
|
||||
|
||||
/* GPP 0 */
|
||||
Name(PS5, Package(){
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APS5, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 28 },
|
||||
Package(){0x0000FFFF, 1, 0, 29 },
|
||||
Package(){0x0000FFFF, 2, 0, 30 },
|
||||
Package(){0x0000FFFF, 3, 0, 31 },
|
||||
})
|
||||
|
||||
/* GPP 1 */
|
||||
Name(PS6, Package(){
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS6, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 32 },
|
||||
Package(){0x0000FFFF, 1, 0, 33 },
|
||||
Package(){0x0000FFFF, 2, 0, 34 },
|
||||
Package(){0x0000FFFF, 3, 0, 35 },
|
||||
})
|
||||
|
||||
/* GPP 2 */
|
||||
Name(PS7, Package(){
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APS7, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 36 },
|
||||
Package(){0x0000FFFF, 1, 0, 37 },
|
||||
Package(){0x0000FFFF, 2, 0, 38 },
|
||||
Package(){0x0000FFFF, 3, 0, 39 },
|
||||
})
|
||||
|
||||
/* GPP 3 */
|
||||
Name(PS8, Package(){
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS8, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 40 },
|
||||
Package(){0x0000FFFF, 1, 0, 41 },
|
||||
Package(){0x0000FFFF, 2, 0, 42 },
|
||||
Package(){0x0000FFFF, 3, 0, 43 },
|
||||
})
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* No SATA functionality */
|
||||
|
|
@ -1,64 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Wake status package */
|
||||
Name(WKST,Package(){Zero, Zero})
|
||||
|
||||
/*
|
||||
* \_PTS - Prepare to Sleep method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2, etc
|
||||
*
|
||||
* Exit:
|
||||
* -none-
|
||||
*
|
||||
* The _PTS control method is executed at the beginning of the sleep process
|
||||
* for S1-S5. The sleeping value is passed to the _PTS control method. This
|
||||
* control method may be executed a relatively long time before entering the
|
||||
* sleep state and the OS may abort the operation without notification to
|
||||
* the ACPI driver. This method cannot modify the configuration or power
|
||||
* state of any device in the system.
|
||||
*/
|
||||
|
||||
External(\_SB.APTS, MethodObj)
|
||||
External(\_SB.AWAK, MethodObj)
|
||||
|
||||
Method(_PTS, 1) {
|
||||
/* DBGO("\\_PTS\n") */
|
||||
/* DBGO("From S0 to S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO("\n") */
|
||||
|
||||
/* Clear wake status structure. */
|
||||
WKST [0] = 0
|
||||
WKST [1] = 0
|
||||
UPWS = 7
|
||||
\_SB.APTS(Arg0)
|
||||
} /* End Method(\_PTS) */
|
||||
|
||||
/*
|
||||
* \_WAK System Wake method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2
|
||||
*
|
||||
* Exit:
|
||||
* Return package of 2 DWords
|
||||
* Dword 1 - Status
|
||||
* 0x00000000 wake succeeded
|
||||
* 0x00000001 Wake was signaled but failed due to lack of power
|
||||
* 0x00000002 Wake was signaled but failed due to thermal condition
|
||||
* Dword 2 - Power Supply state
|
||||
* if non-zero the effective S-state the power supply entered
|
||||
*/
|
||||
Method(\_WAK, 1) {
|
||||
/* DBGO("\\_WAK\n") */
|
||||
/* DBGO("From S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO(" to S0\n") */
|
||||
USBS = 1
|
||||
|
||||
\_SB.AWAK(Arg0)
|
||||
|
||||
Return(WKST)
|
||||
} /* End Method(\_WAK) */
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
/* SPDX-License-Identifier: CC-PDDC */
|
||||
|
||||
/* Please update the license if adding licensable material. */
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
/* SPDX-License-Identifier: CC-PDDC */
|
||||
|
||||
/* Please update the license if adding licensable material. */
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* USB overcurrent mapping pins. */
|
||||
Name(UOM0, 0)
|
||||
Name(UOM1, 2)
|
||||
Name(UOM2, 0)
|
||||
Name(UOM3, 7)
|
||||
Name(UOM4, 2)
|
||||
Name(UOM5, 2)
|
||||
Name(UOM6, 6)
|
||||
Name(UOM7, 2)
|
||||
Name(UOM8, 6)
|
||||
Name(UOM9, 6)
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
Category: mini
|
||||
Board URL: http://www.asrock.com/ipc/overview.asp?Model=IMB-A180
|
||||
ROM package: DIP8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: y
|
||||
Flashrom support: y
|
||||
Release year: 2013
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <amdblocks/acpimmio.h>
|
||||
#include <bootblock_common.h>
|
||||
#include <device/pnp_type.h>
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
#include <superio/winbond/w83627uhg/w83627uhg.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1)
|
||||
|
||||
void bootblock_mainboard_early_init(void)
|
||||
{
|
||||
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
|
||||
pm_write8(0xea, 0x1);
|
||||
|
||||
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
|
||||
misc_write32(0x28, misc_read32(0x28) & 0xfff8ffff);
|
||||
|
||||
/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
|
||||
misc_write32(0x40, misc_read32(0x40) & 0xffffbffb);
|
||||
|
||||
/* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */
|
||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
}
|
||||
|
|
@ -1,45 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <AGESA.h>
|
||||
|
||||
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
|
||||
#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
|
||||
|
||||
//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
|
||||
//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
|
||||
//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_SRAT FALSE
|
||||
#define BLDOPT_REMOVE_WHEA FALSE
|
||||
#define BLDOPT_REMOVE_CRAT TRUE
|
||||
#define BLDOPT_REMOVE_CDIT TRUE
|
||||
|
||||
/* Build configuration values here. */
|
||||
#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0
|
||||
|
||||
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
|
||||
|
||||
#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
|
||||
#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
|
||||
#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
|
||||
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
|
||||
#define BLDCFG_ENABLE_ECC_FEATURE TRUE
|
||||
#define BLDCFG_ECC_SYNC_FLOOD TRUE
|
||||
#define BLDCFG_IOMMU_SUPPORT FALSE
|
||||
|
||||
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
|
||||
|
||||
/* Include the files that instantiate the configuration definitions. */
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuFamRegisters.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "AdvancedApi.h"
|
||||
#include "heapManager.h"
|
||||
#include "CreateStruct.h"
|
||||
#include "cpuFeatures.h"
|
||||
#include "Table.h"
|
||||
#include "cpuEarlyInit.h"
|
||||
#include "cpuLateInit.h"
|
||||
#include "GnbInterface.h"
|
||||
|
||||
#include <PlatformInstall.h>
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
#*****************************************************************************
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#*****************************************************************************
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
444 1 e 1 nmi
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
|
@ -1,94 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip northbridge/amd/agesa/family16kb/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/agesa/family16kb
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x1410 inherit
|
||||
|
||||
chip northbridge/amd/agesa/family16kb
|
||||
device pci 0.0 on end # Root Complex
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
|
||||
device pci 1.1 on end # Internal Multimedia
|
||||
device pci 2.0 on end # PCIe Host Bridge
|
||||
device pci 2.1 on end # x4 PCIe slot
|
||||
device pci 2.2 on end # mPCIe slot
|
||||
device pci 2.3 on end # Realtek NIC
|
||||
device pci 2.4 on end # Edge Connector
|
||||
device pci 2.5 on end # Edge Connector
|
||||
end #chip northbridge/amd/agesa/family16kb
|
||||
|
||||
chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
|
||||
device pci 10.0 on end # XHCI HC0
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on end # SM
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on
|
||||
chip superio/winbond/w83627uhg
|
||||
device pnp 2e.0 off end # FDC
|
||||
device pnp 2e.1 off end # LPT1
|
||||
device pnp 2e.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # KEYBRD
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 on # COM3
|
||||
io 0x60 = 0x3e8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.7 off end # GPIO
|
||||
device pnp 2e.8 off end # WDT
|
||||
device pnp 2e.9 off end # GPIO
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b off end # HWMON
|
||||
device pnp 2e.c off end # PECI
|
||||
device pnp 2e.d on # COM4
|
||||
io 0x60 = 0x2e8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.e on # COM5
|
||||
io 0x60 = 0x3e0
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.f on # COM6
|
||||
io 0x60 = 0x2e0
|
||||
irq 0x70 = 3
|
||||
end
|
||||
end # w83627uhg
|
||||
end # LPC 0x439d
|
||||
device pci 14.7 on end # SD
|
||||
end #chip southbridge/amd/agesa/hudson
|
||||
|
||||
chip northbridge/amd/agesa/family16kb
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 18.5 on end
|
||||
register "spdAddrLookup" = "
|
||||
{
|
||||
{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
|
||||
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
|
||||
}"
|
||||
end
|
||||
|
||||
end #domain
|
||||
end #northbridge/amd/agesa/family16kb/root_complex
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* DefinitionBlock Statement */
|
||||
#include <acpi/acpi.h>
|
||||
DefinitionBlock (
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x00010001 /* OEM Revision */
|
||||
)
|
||||
{ /* Start of ASL file */
|
||||
#include <acpi/dsdt_top.asl>
|
||||
|
||||
/* Globals for the platform */
|
||||
#include "acpi/mainboard.asl"
|
||||
|
||||
/* Describe the USB Overcurrent pins */
|
||||
#include "acpi/usb_oc.asl"
|
||||
|
||||
/* PCI IRQ mapping for the Southbridge */
|
||||
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
|
||||
|
||||
/* Describe the processor tree (\_SB) */
|
||||
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
|
||||
|
||||
/* Contains the supported sleep states for this chipset */
|
||||
#include <southbridge/amd/common/acpi/sleepstates.asl>
|
||||
|
||||
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
|
||||
#include "acpi/sleep.asl"
|
||||
|
||||
/* System Bus */
|
||||
Scope(\_SB) { /* Start \_SB scope */
|
||||
/* global utility methods expected within the \_SB scope */
|
||||
#include <arch/x86/acpi/globutil.asl>
|
||||
|
||||
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
|
||||
#include "acpi/routing.asl"
|
||||
|
||||
Device(PWRB) {
|
||||
Name(_HID, EISAID("PNP0C0C"))
|
||||
Name(_UID, 0xAA)
|
||||
Name(_PRW, Package () {3, 0x04})
|
||||
Name(_STA, 0x0B)
|
||||
}
|
||||
|
||||
Device(PCI0) {
|
||||
/* Describe the AMD Northbridge */
|
||||
#include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>
|
||||
|
||||
/* Describe the AMD Fusion Controller Hub Southbridge */
|
||||
#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
|
||||
}
|
||||
|
||||
/* Describe PCI INT[A-H] for the Southbridge */
|
||||
#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
|
||||
|
||||
} /* End \_SB scope */
|
||||
|
||||
/* Describe SMBUS for the Southbridge */
|
||||
#include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
|
||||
|
||||
/* Define the General Purpose Events for the platform */
|
||||
#include "acpi/gpe.asl"
|
||||
|
||||
/* Define the Thermal zones and methods for the platform */
|
||||
#include "acpi/thermal.asl"
|
||||
}
|
||||
/* End of ASL file */
|
||||
|
|
@ -1,88 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <commonlib/bsd/helpers.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr = ALIGN_UP(addr, 16);
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = 0;
|
||||
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1002;
|
||||
pirq->rtr_device = 0x4384;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "%s done.\n", __func__);
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/device.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
|
||||
static const u8 mainboard_picr_data[0x54] = {
|
||||
0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x03, 0x04, 0x05, 0x07
|
||||
};
|
||||
|
||||
static const u8 mainboard_intr_data[0x54] = {
|
||||
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x10, 0x11, 0x12, 0x13
|
||||
};
|
||||
|
||||
/* PIRQ Setup */
|
||||
static void pirq_setup(void)
|
||||
{
|
||||
intr_data_ptr = mainboard_intr_data;
|
||||
picr_data_ptr = mainboard_picr_data;
|
||||
}
|
||||
|
||||
/**********************************************
|
||||
* enable the dedicated function in mainboard.
|
||||
**********************************************/
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
pirq_setup();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -1,123 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia.h>
|
||||
#include <AGESA.h>
|
||||
#include <console/console.h>
|
||||
#include <northbridge/amd/agesa/BiosCallOuts.h>
|
||||
#include <northbridge/amd/agesa/state_machine.h>
|
||||
#include <FchPlatform.h>
|
||||
#include <option.h>
|
||||
#include <types.h>
|
||||
|
||||
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
|
||||
{
|
||||
{AGESA_DO_RESET, agesa_Reset },
|
||||
{AGESA_READ_SPD, agesa_ReadSpd },
|
||||
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
|
||||
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
|
||||
{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
|
||||
{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
|
||||
{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
|
||||
{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
|
||||
};
|
||||
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
|
||||
|
||||
/**
|
||||
* CODEC Initialization Table for Azalia HD Audio using Realtek ALC887-VD chip (from linux, running under vendor bios)
|
||||
*/
|
||||
const CODEC_ENTRY Alc887_VerbTbl[] =
|
||||
{
|
||||
{ 0x11, 0x40330000 },
|
||||
{ 0x12, 0x411111f0 },
|
||||
{ 0x14, 0x01014010 },
|
||||
{ 0x15, 0x411111f0 },
|
||||
{ 0x16, 0x411111f0 },
|
||||
{ 0x17, 0x411111f0 },
|
||||
{ 0x18, 0x01a19030 },
|
||||
{ 0x19, 0x02a19040 },
|
||||
{ 0x1a, 0x0181303f },
|
||||
{ 0x1b, 0x02214020 },
|
||||
{ 0x1c, 0x411111f0 },
|
||||
{ 0x1d, 0x4024c601 },
|
||||
{ 0x1e, 0x411111f0 },
|
||||
{ 0x1f, 0x411111f0 }
|
||||
};
|
||||
|
||||
static const CODEC_TBL_LIST CodecTableList[] =
|
||||
{
|
||||
{0x10ec0887, (CODEC_ENTRY*)&Alc887_VerbTbl[0]},
|
||||
{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
|
||||
};
|
||||
|
||||
#define FAN_INPUT_INTERNAL_DIODE 0
|
||||
#define FAN_INPUT_TEMP0 1
|
||||
#define FAN_INPUT_TEMP1 2
|
||||
#define FAN_INPUT_TEMP2 3
|
||||
#define FAN_INPUT_TEMP3 4
|
||||
#define FAN_INPUT_TEMP0_FILTER 5
|
||||
#define FAN_INPUT_ZERO 6
|
||||
#define FAN_INPUT_DISABLED 7
|
||||
|
||||
#define FAN_AUTOMODE (1 << 0)
|
||||
#define FAN_LINEARMODE (1 << 1)
|
||||
#define FAN_STEPMODE ~(1 << 1)
|
||||
#define FAN_POLARITY_HIGH (1 << 2)
|
||||
#define FAN_POLARITY_LOW ~(1 << 2)
|
||||
|
||||
/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
|
||||
#define FREQ_28KHZ 0x0
|
||||
#define FREQ_25KHZ 0x1
|
||||
#define FREQ_23KHZ 0x2
|
||||
#define FREQ_21KHZ 0x3
|
||||
#define FREQ_29KHZ 0x4
|
||||
#define FREQ_18KHZ 0x5
|
||||
#define FREQ_100HZ 0xF7
|
||||
#define FREQ_87HZ 0xF8
|
||||
#define FREQ_58HZ 0xF9
|
||||
#define FREQ_44HZ 0xFA
|
||||
#define FREQ_35HZ 0xFB
|
||||
#define FREQ_29HZ 0xFC
|
||||
#define FREQ_22HZ 0xFD
|
||||
#define FREQ_14HZ 0xFE
|
||||
#define FREQ_11HZ 0xFF
|
||||
|
||||
void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
|
||||
{
|
||||
FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
|
||||
FchParams_reset->Mode = 6;
|
||||
|
||||
/* Read SATA speed setting from CMOS */
|
||||
FchParams_reset->SataSetMaxGen2 = get_uint_option("sata_speed", 0);
|
||||
printk(BIOS_DEBUG, "Force SATA 3Gbps mode = %x\n", FchParams_reset->SataSetMaxGen2);
|
||||
}
|
||||
|
||||
void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
|
||||
{
|
||||
/* Azalia Controller OEM Codec Table Pointer */
|
||||
FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
|
||||
|
||||
/* Fan Control */
|
||||
FchParams_env->Imc.ImcEnable = FALSE;
|
||||
FchParams_env->Hwm.HwMonitorEnable = FALSE;
|
||||
FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
|
||||
|
||||
/* Read SATA controller mode from CMOS */
|
||||
FchParams_env->Sata.SataClass = get_uint_option("sata_mode", 0);
|
||||
|
||||
switch ((SATA_CLASS)FchParams_env->Sata.SataClass) {
|
||||
case SataLegacyIde:
|
||||
case SataRaid:
|
||||
case SataAhci:
|
||||
case SataAhci7804:
|
||||
FchParams_env->Sata.SataIdeMode = FALSE;
|
||||
printk(BIOS_DEBUG, "AHCI or RAID or IDE = %x\n", FchParams_env->Sata.SataClass);
|
||||
break;
|
||||
|
||||
case SataIde2Ahci:
|
||||
case SataIde2Ahci7804:
|
||||
default: /* SataNativeIde */
|
||||
FchParams_env->Sata.SataIdeMode = TRUE;
|
||||
printk(BIOS_DEBUG, "IDE2AHCI = %x\n", FchParams_env->Sata.SataClass);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -1,53 +0,0 @@
|
|||
if BOARD_ASUS_AM1I_A
|
||||
|
||||
config IGNORE_IASL_MISSING_DEPENDENCY
|
||||
def_bool y
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select BOARD_ROMSIZE_KB_8192
|
||||
select CPU_AMD_AGESA_FAMILY16_KB
|
||||
select FORCE_AM1_SOCKET_SUPPORT
|
||||
select GFXUMA
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_CMOS_DEFAULT
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
|
||||
select SOUTHBRIDGE_AMD_AGESA_YANGTZE
|
||||
select DEFAULT_POST_ON_LPC
|
||||
select SUPERIO_ITE_IT8623E
|
||||
select MEMORY_MAPPED_TPM
|
||||
|
||||
config MAINBOARD_DIR
|
||||
default "asus/am1i-a"
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
default "AM1I-A"
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
default 0x200000
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 10
|
||||
|
||||
config ONBOARD_VGA_IS_PRIMARY
|
||||
bool
|
||||
default y
|
||||
|
||||
config HUDSON_LEGACY_FREE
|
||||
bool
|
||||
default n
|
||||
|
||||
config HUDSON_IMC_FWM
|
||||
bool
|
||||
default n
|
||||
|
||||
endif # BOARD_ASUS_AM1I_A
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config BOARD_ASUS_AM1I_A
|
||||
bool "AM1I-A"
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
bootblock-y += bootblock.c
|
||||
|
||||
romstage-y += buildOpts.c
|
||||
romstage-y += BiosCallOuts.c
|
||||
romstage-y += OemCustomize.c
|
||||
|
||||
ramstage-y += buildOpts.c
|
||||
ramstage-y += BiosCallOuts.c
|
||||
ramstage-y += OemCustomize.c
|
||||
|
|
@ -1,143 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <AGESA.h>
|
||||
#include <PlatformMemoryConfiguration.h>
|
||||
|
||||
#include <northbridge/amd/agesa/state_machine.h>
|
||||
|
||||
static const PCIe_PORT_DESCRIPTOR PortList[] = {
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x01, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x02, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x03, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x04, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x05, 0)
|
||||
}
|
||||
};
|
||||
|
||||
static const PCIe_DDI_DESCRIPTOR DdiList[] = {
|
||||
/* DP0 to HDMI */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
|
||||
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
|
||||
},
|
||||
/* DP1 to DVI-D */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
|
||||
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeSingleLinkDVI, Aux2, Hdp2)
|
||||
},
|
||||
/* DP2 to VGA */
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
|
||||
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3)
|
||||
},
|
||||
};
|
||||
|
||||
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
|
||||
.Flags = DESCRIPTOR_TERMINATE_LIST,
|
||||
.SocketId = 0,
|
||||
.PciePortList = PortList,
|
||||
.DdiLinkList = DdiList
|
||||
};
|
||||
|
||||
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
|
||||
{
|
||||
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
|
||||
|
||||
FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
|
||||
FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE);
|
||||
|
||||
FchReset->SataEnable = 1;
|
||||
FchReset->IdeEnable = 0;
|
||||
}
|
||||
|
||||
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
|
||||
{
|
||||
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* CUSTOMER OVERRIDES MEMORY TABLE
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
|
||||
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
|
||||
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
|
||||
* use its default conservative settings.
|
||||
*/
|
||||
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
|
||||
#define SEED_A 0x12
|
||||
HW_RXEN_SEED(
|
||||
ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
|
||||
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
|
||||
SEED_A),
|
||||
|
||||
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
|
||||
NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
|
||||
MOTHER_BOARD_LAYERS(LAYERS_4),
|
||||
|
||||
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
|
||||
CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
|
||||
ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
|
||||
CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
|
||||
|
||||
PSO_END
|
||||
};
|
||||
|
||||
void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
|
||||
{
|
||||
InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
|
||||
}
|
||||
|
||||
void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
|
||||
{
|
||||
/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
|
||||
InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
|
||||
}
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* IDS Option File
|
||||
*
|
||||
* This file is used to switch on/off IDS features.
|
||||
*
|
||||
*/
|
||||
#ifndef _OPTION_IDS_H_
|
||||
#define _OPTION_IDS_H_
|
||||
|
||||
/**
|
||||
*
|
||||
* This file generates the defaults tables for the Integrated Debug Support
|
||||
* Module. The documented build options are imported from a user controlled
|
||||
* file for processing. The build options for the Integrated Debug Support
|
||||
* Module are listed below:
|
||||
*
|
||||
* IDSOPT_IDS_ENABLED
|
||||
* IDSOPT_ERROR_TRAP_ENABLED
|
||||
* IDSOPT_CONTROL_ENABLED
|
||||
* IDSOPT_TRACING_ENABLED
|
||||
* IDSOPT_PERF_ANALYSIS
|
||||
* IDSOPT_ASSERT_ENABLED
|
||||
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
|
||||
*
|
||||
**/
|
||||
|
||||
#define IDSOPT_IDS_ENABLED TRUE
|
||||
//#define IDSOPT_CONTROL_ENABLED TRUE
|
||||
//#define IDSOPT_TRACING_ENABLED TRUE
|
||||
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
|
||||
//#define IDSOPT_PERF_ANALYSIS TRUE
|
||||
#define IDSOPT_ASSERT_ENABLED TRUE
|
||||
|
||||
#endif
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
|
||||
/* AcpiGpe0Blk */
|
||||
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
|
||||
Field(GP0B, ByteAcc, NoLock, Preserve) {
|
||||
, 11,
|
||||
USBS, 1,
|
||||
}
|
||||
|
|
@ -1,162 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - F16 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */
|
||||
/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
|
||||
Package(){0x0001FFFF, 0, INTA, 0 },
|
||||
Package(){0x0001FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridges */
|
||||
Package(){0x0002FFFF, 0, INTA, 0 },
|
||||
Package(){0x0002FFFF, 1, INTB, 0 },
|
||||
Package(){0x0002FFFF, 2, INTC, 0 },
|
||||
Package(){0x0002FFFF, 3, INTD, 0 },
|
||||
|
||||
/* FCH devices */
|
||||
/* Bus 0, Dev 14 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
|
||||
/* Bus 0, Dev 12 Func 0 - USB: OHCI */
|
||||
/* Bus 0, Dev 12 Func 2 - USB: EHCI */
|
||||
Package(){0x0012FFFF, 0, INTC, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 13 Func 0 - USB: OHCI */
|
||||
/* Bus 0, Dev 13 Func 2 - USB: EHCI */
|
||||
Package(){0x0013FFFF, 0, INTC, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 16 Func 0 - USB: OHCI */
|
||||
/* Bus 0, Dev 16 Func 2 - USB: EHCI */
|
||||
Package(){0x0016FFFF, 0, INTC, 0 },
|
||||
Package(){0x0016FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
|
||||
Package(){0x0010FFFF, 0, INTC, 0 },
|
||||
Package(){0x0010FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 11 - SATA controller */
|
||||
Package(){0x0011FFFF, 0, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - F16 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */
|
||||
/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
|
||||
Package(){0x0001FFFF, 0, 0, 44 },
|
||||
Package(){0x0001FFFF, 1, 0, 45 },
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridges */
|
||||
Package(){0x0002FFFF, 0, 0, 24 },
|
||||
Package(){0x0002FFFF, 1, 0, 25 },
|
||||
Package(){0x0002FFFF, 2, 0, 26 },
|
||||
Package(){0x0002FFFF, 3, 0, 27 },
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 12 Func 0 - USB: OHCI */
|
||||
/* Bus 0, Dev 12 Func 1 - USB: EHCI */
|
||||
Package(){0x0012FFFF, 0, 0, 18 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 13 Func 0 - USB: OHCI */
|
||||
/* Bus 0, Dev 13 Func 1 - USB: EHCI */
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 16 Func 0 - USB: OHCI */
|
||||
/* Bus 0, Dev 16 Func 1 - USB: EHCI */
|
||||
Package(){0x0016FFFF, 0, 0, 18 },
|
||||
Package(){0x0016FFFF, 1, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
|
||||
Package(){0x0010FFFF, 0, 0, 18 },
|
||||
Package(){0x0010FFFF, 1, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 11 - SATA controller */
|
||||
Package(){0x0011FFFF, 0, 0, 19 },
|
||||
})
|
||||
|
||||
/* GPP 0 - PCIe 4x slot */
|
||||
Name(PS4, Package(){
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS4, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 24 },
|
||||
Package(){0x0000FFFF, 1, 0, 25 },
|
||||
Package(){0x0000FFFF, 2, 0, 26 },
|
||||
Package(){0x0000FFFF, 3, 0, 27 },
|
||||
})
|
||||
|
||||
/* GPP 1 - not used */
|
||||
Name(PS5, Package(){
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APS5, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 28 },
|
||||
Package(){0x0000FFFF, 1, 0, 29 },
|
||||
Package(){0x0000FFFF, 2, 0, 30 },
|
||||
Package(){0x0000FFFF, 3, 0, 31 },
|
||||
})
|
||||
|
||||
/* GPP 2 - not used */
|
||||
Name(PS6, Package(){
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS6, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 32 },
|
||||
Package(){0x0000FFFF, 1, 0, 33 },
|
||||
Package(){0x0000FFFF, 2, 0, 34 },
|
||||
Package(){0x0000FFFF, 3, 0, 35 },
|
||||
})
|
||||
|
||||
/* GPP 3 - not used */
|
||||
Name(PS7, Package(){
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APS7, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 36 },
|
||||
Package(){0x0000FFFF, 1, 0, 37 },
|
||||
Package(){0x0000FFFF, 2, 0, 38 },
|
||||
Package(){0x0000FFFF, 3, 0, 39 },
|
||||
})
|
||||
|
||||
/* GPP 4 - Realtek GBE */
|
||||
Name(PS8, Package(){
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APS8, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 40 },
|
||||
Package(){0x0000FFFF, 1, 0, 41 },
|
||||
Package(){0x0000FFFF, 2, 0, 42 },
|
||||
Package(){0x0000FFFF, 3, 0, 43 },
|
||||
})
|
||||
|
|
@ -1,118 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Name(STTM, Buffer(20) {
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x1f, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
/* Start by clearing the PhyRdyChg bits */
|
||||
Method(_INI) {
|
||||
\_GPE._L1F()
|
||||
}
|
||||
|
||||
Device(PMRY)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(PMST) {
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (P0IS > 0) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
}/* end of PMST */
|
||||
|
||||
Device(PSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (P1IS > 0) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of PSLA */
|
||||
} /* end of PMRY */
|
||||
|
||||
Device(SEDY)
|
||||
{
|
||||
Name(_ADR, 1) /* IDE Scondary Channel */
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(SMST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (P2IS > 0) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SMST */
|
||||
|
||||
Device(SSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (P3IS > 0) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SSLA */
|
||||
} /* end of SEDY */
|
||||
|
||||
/* SATA Hot Plug Support */
|
||||
Scope(\_GPE) {
|
||||
Method(_L1F,0x0,NotSerialized) {
|
||||
if (\_SB.P0PR) {
|
||||
if (\_SB.P0IS > 0) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
\_SB.P0PR = 1
|
||||
}
|
||||
|
||||
if (\_SB.P1PR) {
|
||||
if (\_SB.P1IS > 0) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
\_SB.P1PR = 1
|
||||
}
|
||||
|
||||
if (\_SB.P2PR) {
|
||||
if (\_SB.P2IS > 0) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
\_SB.P2PR = 1
|
||||
}
|
||||
|
||||
if (\_SB.P3PR) {
|
||||
if (\_SB.P3IS > 0) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
\_SB.P3PR = 1
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,64 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Wake status package */
|
||||
Name(WKST,Package(){Zero, Zero})
|
||||
|
||||
/*
|
||||
* \_PTS - Prepare to Sleep method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2, etc
|
||||
*
|
||||
* Exit:
|
||||
* -none-
|
||||
*
|
||||
* The _PTS control method is executed at the beginning of the sleep process
|
||||
* for S1-S5. The sleeping value is passed to the _PTS control method. This
|
||||
* control method may be executed a relatively long time before entering the
|
||||
* sleep state and the OS may abort the operation without notification to
|
||||
* the ACPI driver. This method cannot modify the configuration or power
|
||||
* state of any device in the system.
|
||||
*/
|
||||
|
||||
External(\_SB.APTS, MethodObj)
|
||||
External(\_SB.AWAK, MethodObj)
|
||||
|
||||
Method(_PTS, 1) {
|
||||
/* DBGO("\\_PTS\n") */
|
||||
/* DBGO("From S0 to S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO("\n") */
|
||||
|
||||
/* Clear wake status structure. */
|
||||
WKST [0] = 0
|
||||
WKST [1] = 0
|
||||
UPWS = 7
|
||||
\_SB.APTS(Arg0)
|
||||
} /* End Method(\_PTS) */
|
||||
|
||||
/*
|
||||
* \_WAK System Wake method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2
|
||||
*
|
||||
* Exit:
|
||||
* Return package of 2 DWords
|
||||
* Dword 1 - Status
|
||||
* 0x00000000 wake succeeded
|
||||
* 0x00000001 Wake was signaled but failed due to lack of power
|
||||
* 0x00000002 Wake was signaled but failed due to thermal condition
|
||||
* Dword 2 - Power Supply state
|
||||
* if non-zero the effective S-state the power supply entered
|
||||
*/
|
||||
Method(\_WAK, 1) {
|
||||
/* DBGO("\\_WAK\n") */
|
||||
/* DBGO("From S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO(" to S0\n") */
|
||||
USBS = 1
|
||||
|
||||
\_SB.AWAK(Arg0)
|
||||
|
||||
Return(WKST)
|
||||
} /* End Method(\_WAK) */
|
||||
|
|
@ -1,96 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
// Scope is \_SB.PCI0.LPCB
|
||||
|
||||
// Values, defined here, must match settings in devicetree.cb
|
||||
|
||||
Device (PS2M) {
|
||||
Name (_HID, EisaId ("PNP0F13"))
|
||||
Name (_CRS, ResourceTemplate () {
|
||||
IRQNoFlags () {12}
|
||||
})
|
||||
}
|
||||
|
||||
Device (PS2K) {
|
||||
Name (_HID, EisaId ("PNP0303"))
|
||||
Name (_CRS, ResourceTemplate () {
|
||||
IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
|
||||
IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
|
||||
IRQNoFlags () {1}
|
||||
})
|
||||
}
|
||||
|
||||
Device (COM1) {
|
||||
Name (_HID, EISAID ("PNP0501"))
|
||||
Name (_UID, 1)
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
|
||||
IRQNoFlags () {4}
|
||||
})
|
||||
Name (_PRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
|
||||
IRQNoFlags () {4}
|
||||
})
|
||||
}
|
||||
|
||||
Device (COM2) {
|
||||
Name (_HID, EISAID ("PNP0501"))
|
||||
Name (_UID, 2)
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
|
||||
IRQNoFlags () {3}
|
||||
})
|
||||
Name (_PRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
|
||||
IRQNoFlags () {3}
|
||||
})
|
||||
}
|
||||
|
||||
Device (LPT1) {
|
||||
Name (_HID, EISAID ("PNP0401"))
|
||||
Name (_UID, 1)
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0378, 0x0378, 0x04, 0x08)
|
||||
IO (Decode16, 0x0778, 0x0778, 0x04, 0x08)
|
||||
IRQNoFlags () {5}
|
||||
})
|
||||
Name (_PRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0378, 0x0378, 0x04, 0x08)
|
||||
IO (Decode16, 0x0778, 0x0778, 0x04, 0x08)
|
||||
IRQNoFlags () {5}
|
||||
})
|
||||
}
|
||||
|
||||
Device (ENVC) {
|
||||
Name (_HID, EISAID ("PNP0C02"))
|
||||
Name (_UID, 1)
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0230, 0x0230, 0x04, 0x10)
|
||||
IO (Decode16, 0x0290, 0x0290, 0x04, 0x10)
|
||||
})
|
||||
Name (_PRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0230, 0x0230, 0x04, 0x10)
|
||||
IO (Decode16, 0x0290, 0x0290, 0x04, 0x10)
|
||||
})
|
||||
}
|
||||
|
||||
Device (GPIC) {
|
||||
Name (_HID, EISAID ("PNP0C02"))
|
||||
Name (_UID, 2)
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0300, 0x0300, 0x04, 0x20)
|
||||
})
|
||||
Name (_PRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0300, 0x0300, 0x04, 0x20)
|
||||
})
|
||||
}
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
Category: mini
|
||||
Board URL: https://www.asus.com/us/Motherboards/AM1IA/
|
||||
ROM package: DIP8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: y
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <amdblocks/acpimmio.h>
|
||||
#include <arch/io.h>
|
||||
#include <bootblock_common.h>
|
||||
#include <device/pnp_ops.h>
|
||||
#include <superio/ite/common/ite.h>
|
||||
#include <superio/ite/it8623e/it8623e.h>
|
||||
|
||||
#if CONFIG_UART_FOR_CONSOLE == 0
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, IT8623E_SP1)
|
||||
#elif CONFIG_UART_FOR_CONSOLE == 1
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, IT8623E_SP2)
|
||||
#else
|
||||
#error "Invalid value for CONFIG_UART_FOR_CONSOLE"
|
||||
#endif
|
||||
|
||||
#define GPIO_DEV PNP_DEV(0x2e, IT8623E_GPIO)
|
||||
#define CLKIN_DEV PNP_DEV(0x2e, IT8623E_GPIO)
|
||||
#define ENVC_DEV PNP_DEV(0x2e, IT8623E_EC)
|
||||
|
||||
/* Sets up EC configuration as per vendor defaults */
|
||||
static void ite_evc_conf(pnp_devfn_t dev)
|
||||
{
|
||||
pnp_set_enable(dev, 0);
|
||||
ite_reg_write(dev, 0x70, 0x00);
|
||||
ite_reg_write(dev, 0xf0, 0x00);
|
||||
ite_reg_write(dev, 0xf1, 0x00);
|
||||
ite_reg_write(dev, 0xf2, 0x06);
|
||||
ite_reg_write(dev, 0xf3, 0x00);
|
||||
ite_reg_write(dev, 0xf4, 0x00);
|
||||
ite_reg_write(dev, 0xf5, 0x36);
|
||||
ite_reg_write(dev, 0xf6, 0x03);
|
||||
ite_reg_write(dev, 0xf9, 0x48);
|
||||
ite_reg_write(dev, 0xfa, 0x00);
|
||||
ite_reg_write(dev, 0xfb, 0x10);
|
||||
pnp_set_enable(dev, 1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Sets up GPIO configuration as per vendor defaults
|
||||
* SIO defaults are unknown therefore all GPIO pins are configured
|
||||
*/
|
||||
static void ite_gpio_conf(pnp_devfn_t dev)
|
||||
{
|
||||
ite_reg_write(dev, 0x23, 0x08);
|
||||
ite_reg_write(dev, 0x25, 0x10);
|
||||
ite_reg_write(dev, 0x26, 0x00);
|
||||
ite_reg_write(dev, 0x27, 0x80);
|
||||
ite_reg_write(dev, 0x28, 0x45);
|
||||
ite_reg_write(dev, 0x29, 0x00);
|
||||
ite_reg_write(dev, 0x2a, 0x00);
|
||||
ite_reg_write(dev, 0x2b, 0x48);
|
||||
ite_reg_write(dev, 0x2c, 0x10);
|
||||
ite_reg_write(dev, 0x2d, 0x80);
|
||||
ite_reg_write(dev, 0x71, 0x00);
|
||||
ite_reg_write(dev, 0x72, 0x00);
|
||||
ite_reg_write(dev, 0x73, 0x38);
|
||||
ite_reg_write(dev, 0x74, 0x00);
|
||||
ite_reg_write(dev, 0xb0, 0x00);
|
||||
ite_reg_write(dev, 0xb1, 0x00);
|
||||
ite_reg_write(dev, 0xb2, 0x00);
|
||||
ite_reg_write(dev, 0xb3, 0x00);
|
||||
ite_reg_write(dev, 0xb4, 0x00);
|
||||
ite_reg_write(dev, 0xb8, 0x00);
|
||||
ite_reg_write(dev, 0xb9, 0x00);
|
||||
ite_reg_write(dev, 0xba, 0x00);
|
||||
ite_reg_write(dev, 0xbb, 0x00);
|
||||
ite_reg_write(dev, 0xbc, 0x00);
|
||||
ite_reg_write(dev, 0xbd, 0x00);
|
||||
ite_reg_write(dev, 0xc0, 0x01);
|
||||
ite_reg_write(dev, 0xc1, 0x00);
|
||||
ite_reg_write(dev, 0xc2, 0x00);
|
||||
ite_reg_write(dev, 0xc3, 0x00);
|
||||
ite_reg_write(dev, 0xc4, 0x00);
|
||||
ite_reg_write(dev, 0xc8, 0x01);
|
||||
ite_reg_write(dev, 0xc9, 0x00);
|
||||
ite_reg_write(dev, 0xca, 0x00);
|
||||
ite_reg_write(dev, 0xcb, 0x00);
|
||||
ite_reg_write(dev, 0xcc, 0x00);
|
||||
ite_reg_write(dev, 0xcd, 0x20);
|
||||
ite_reg_write(dev, 0xce, 0x00);
|
||||
ite_reg_write(dev, 0xcf, 0x00);
|
||||
ite_reg_write(dev, 0xe0, 0x00);
|
||||
ite_reg_write(dev, 0xe1, 0x00);
|
||||
ite_reg_write(dev, 0xe2, 0x00);
|
||||
ite_reg_write(dev, 0xe3, 0x00);
|
||||
ite_reg_write(dev, 0xe4, 0x00);
|
||||
ite_reg_write(dev, 0xe9, 0x21);
|
||||
ite_reg_write(dev, 0xf0, 0x00);
|
||||
ite_reg_write(dev, 0xf1, 0x00);
|
||||
ite_reg_write(dev, 0xf2, 0x00);
|
||||
ite_reg_write(dev, 0xf3, 0x00);
|
||||
ite_reg_write(dev, 0xf4, 0x00);
|
||||
ite_reg_write(dev, 0xf5, 0x00);
|
||||
ite_reg_write(dev, 0xf6, 0x00);
|
||||
ite_reg_write(dev, 0xf7, 0x00);
|
||||
ite_reg_write(dev, 0xf8, 0x00);
|
||||
ite_reg_write(dev, 0xf9, 0x00);
|
||||
ite_reg_write(dev, 0xfa, 0x00);
|
||||
ite_reg_write(dev, 0xfb, 0x00);
|
||||
}
|
||||
|
||||
void bootblock_mainboard_early_init(void)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
|
||||
pm_write8(0xea, 0x1);
|
||||
|
||||
/* Configure ClkDrvStr1 settings */
|
||||
misc_write32(0x24, 0x030800aa);
|
||||
|
||||
/* Configure MiscClkCntl1 settings */
|
||||
misc_write32(0x40, 0x000c4050);
|
||||
|
||||
/* Configure SIO as made under vendor BIOS */
|
||||
ite_gpio_conf(GPIO_DEV);
|
||||
ite_evc_conf(ENVC_DEV);
|
||||
|
||||
/* Enable serial output on it8623e */
|
||||
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
|
||||
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
ite_kill_watchdog(GPIO_DEV);
|
||||
|
||||
/*
|
||||
* On Larne, after LpcClkDrvSth is set, it needs some time to be stable,
|
||||
* because of the buffer ICS551M
|
||||
*/
|
||||
for (i = 0; i < 200000; i++)
|
||||
inb(0xcd6);
|
||||
}
|
||||
|
|
@ -1,59 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <vendorcode/amd/agesa/f16kb/AGESA.h>
|
||||
|
||||
/* Include the files that instantiate the configuration definitions. */
|
||||
#include <vendorcode/amd/agesa/f16kb/Include/AdvancedApi.h>
|
||||
#include <vendorcode/amd/agesa/f16kb/Include/GnbInterface.h>
|
||||
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h>
|
||||
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h>
|
||||
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/Family/cpuFamRegisters.h>
|
||||
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.h>
|
||||
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h>
|
||||
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.h>
|
||||
/* AGESA nonsense: the next three headers depend on heapManager.h */
|
||||
#include <vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.h>
|
||||
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h>
|
||||
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h>
|
||||
|
||||
/* Select the CPU family */
|
||||
#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
|
||||
|
||||
/* Select the CPU socket type */
|
||||
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
|
||||
|
||||
//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
|
||||
//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
|
||||
//#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
|
||||
//#define BLDOPT_REMOVE_SRAT FALSE
|
||||
#define BLDOPT_REMOVE_WHEA FALSE
|
||||
#define BLDOPT_REMOVE_CRAT TRUE
|
||||
#define BLDOPT_REMOVE_CDIT TRUE
|
||||
|
||||
/* Build configuration values here. */
|
||||
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP
|
||||
|
||||
#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY
|
||||
#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE
|
||||
#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
|
||||
#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
|
||||
#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE
|
||||
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE
|
||||
#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY
|
||||
#define BLDCFG_IGNORE_SPD_CHECKSUM TRUE
|
||||
#define BLDCFG_ENABLE_ECC_FEATURE FALSE
|
||||
#define BLDCFG_ECC_SYNC_FLOOD FALSE
|
||||
|
||||
/*
|
||||
* Specify the default values for the VRM controlling the VDDNB plane.
|
||||
* If not specified, the values used for the core VRM will be applied
|
||||
*/
|
||||
#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0
|
||||
|
||||
#define BLDCFG_IOMMU_SUPPORT FALSE
|
||||
|
||||
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
|
||||
|
||||
/* AGESA nonsense: this header depends on the definitions above */
|
||||
#include <PlatformInstall.h>
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
boot_option=Fallback
|
||||
debug_level=Debug
|
||||
sata_mode=IDE
|
||||
sata_speed=6Gbps
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
#*****************************************************************************
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#*****************************************************************************
|
||||
|
||||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 r 0 reboot_counter
|
||||
#400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 r 0 boot_index
|
||||
432 8 r 0 boot_countdown
|
||||
440 8 e 10 sata_mode
|
||||
448 8 e 11 sata_speed
|
||||
#728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
#1 0 Disable
|
||||
#1 1 Enable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
10 0 IDE
|
||||
10 2 AHCI
|
||||
11 1 3Gbps
|
||||
11 0 6Gbps
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 455 984
|
||||
|
|
@ -1,91 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip northbridge/amd/agesa/family16kb/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/agesa/family16kb
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1043 0x8623 inherit
|
||||
chip northbridge/amd/agesa/family16kb
|
||||
device pci 0.0 on end # Root Complex
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
|
||||
device pci 1.1 on end # Internal Multimedia
|
||||
device pci 2.0 on end # Host Bridge
|
||||
device pci 2.1 on end # x4 PCIe slot
|
||||
device pci 2.2 off end # GPP Bridge 1 - not used
|
||||
device pci 2.3 off end # GPP Bridge 2 - not used
|
||||
device pci 2.4 off end # GPP Bridge 3 - not used
|
||||
device pci 2.5 on end # Realtek GBE
|
||||
end #chip northbridge/amd/agesa/family16kb
|
||||
|
||||
chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
|
||||
device pci 10.0 on end # XHCI HC0
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on end # SM
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on # LPC 0x439d
|
||||
chip superio/ite/it8623e
|
||||
device pnp 2e.0 off end # FDC - not used
|
||||
device pnp 2e.1 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.2 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
io 0x62 = 0x778 # for ECP mode
|
||||
irq 0x70 = 5
|
||||
drq 0x74 = 3
|
||||
end
|
||||
device pnp 2e.4 on # EC
|
||||
io 0x60 = 0x290
|
||||
io 0x62 = 0x230
|
||||
end
|
||||
device pnp 2e.5 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.6 on # PS/2 mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
io 0x60 = 0x320
|
||||
io 0x62 = 0x300
|
||||
io 0x64 = 0x321
|
||||
end
|
||||
end #superio/ite/it8623e
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 4e.0 on end # TPM module
|
||||
end
|
||||
end #device pci 14.3 # LPC
|
||||
device pci 14.7 off end # SD - no card reader present
|
||||
device pci 16.0 on end # OHCI USB
|
||||
device pci 16.2 on end # EHCI USB
|
||||
end #chip southbridge/amd/agesa/hudson
|
||||
|
||||
chip northbridge/amd/agesa/family16kb
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 18.5 on end
|
||||
register "spdAddrLookup" = "
|
||||
{
|
||||
{ {0xA0, 0xA2} },
|
||||
}"
|
||||
end
|
||||
|
||||
end #domain
|
||||
end #northbridge/amd/agesa/family16kb/root_complex
|
||||
|
|
@ -1,62 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* DefinitionBlock Statement */
|
||||
#include <acpi/acpi.h>
|
||||
DefinitionBlock (
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x00010001 /* OEM Revision */
|
||||
)
|
||||
{ /* Start of ASL file */
|
||||
#include <acpi/dsdt_top.asl>
|
||||
|
||||
/* Globals for the platform */
|
||||
#include "acpi/mainboard.asl"
|
||||
|
||||
/* PCI IRQ mapping for the Southbridge */
|
||||
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
|
||||
|
||||
/* Describe the processor tree (\_SB) */
|
||||
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
|
||||
|
||||
/* Contains the supported sleep states for this chipset */
|
||||
#include <southbridge/amd/common/acpi/sleepstates.asl>
|
||||
|
||||
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
|
||||
#include "acpi/sleep.asl"
|
||||
|
||||
/* System Bus */
|
||||
Scope(\_SB) { /* Start \_SB scope */
|
||||
/* global utility methods expected within the \_SB scope */
|
||||
#include <arch/x86/acpi/globutil.asl>
|
||||
|
||||
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
|
||||
#include "acpi/routing.asl"
|
||||
|
||||
Device(PWRB) {
|
||||
Name(_HID, EISAID("PNP0C0C"))
|
||||
Name(_UID, 0xAA)
|
||||
Name(_PRW, Package () {3, 0x04})
|
||||
Name(_STA, 0x0B)
|
||||
}
|
||||
|
||||
Device(PCI0) {
|
||||
/* Describe the AMD Northbridge */
|
||||
#include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>
|
||||
|
||||
/* Describe the AMD Fusion Controller Hub Southbridge */
|
||||
#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
|
||||
}
|
||||
|
||||
/* Describe PCI INT[A-H] for the Southbridge */
|
||||
#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
|
||||
|
||||
} /* End \_SB scope */
|
||||
|
||||
/* Describe SMBUS for the Southbridge */
|
||||
#include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
|
||||
}
|
||||
/* End of ASL file */
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
|
||||
0x00, /* Interrupt router bus */
|
||||
(0x14 << 3) | 0x3, /* Interrupt router dev */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1002, /* Vendor */
|
||||
0x439d, /* Device */
|
||||
0, /* Miniport */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x3b, /* Checksum (has to be set to some value that
|
||||
* would give 0 after the sum of all bytes
|
||||
* for this structure (including checksum).
|
||||
*/
|
||||
/* clang-format off */
|
||||
{
|
||||
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00, (0x01 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
|
||||
{0x00, (0x02 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0},
|
||||
{0x00, (0x10 << 3) | 0x0, {{0x03, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
|
||||
{0x00, (0x11 << 3) | 0x0, {{0x04, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
|
||||
{0x00, (0x12 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
|
||||
{0x00, (0x13 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
|
||||
{0x00, (0x14 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0},
|
||||
{0x00, (0x16 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
|
||||
{0x01, (0x00 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0},
|
||||
{0x02, (0x00 << 3) | 0x0, {{0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
|
||||
}
|
||||
/* clang-format on */
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
||||
|
|
@ -1,86 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/device.h>
|
||||
#include <southbridge/amd/agesa/hudson/pci_devs.h>
|
||||
#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <northbridge/amd/agesa/family16kb/pci_devs.h>
|
||||
|
||||
static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
|
||||
/* INTA# - INTH# */
|
||||
[0x00] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F,
|
||||
/* Misc-nil,0,1,2, INT from Serial irq */
|
||||
[0x08] = 0x5A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
|
||||
/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
|
||||
[0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,
|
||||
/* IMC INT0 - 5 */
|
||||
[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
|
||||
/* USB Devs 18/19/22 INTA-B */
|
||||
[0x30] = 0x05,0x04,0x05,0x04,0x05,0x04,0x1F,0x1F,
|
||||
/* RSVD, SATA */
|
||||
[0x40] = 0x1F, 0x07
|
||||
};
|
||||
|
||||
static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
|
||||
/* INTA# - INTH# */
|
||||
[0x00] = 0x10,0x11,0x12,0x13,0x1F,0x1F,0x1F,0x1F,
|
||||
/* Misc-nil,0,1,2, INT from Serial irq */
|
||||
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
|
||||
/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
|
||||
[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x1F,
|
||||
/* IMC INT0 - 5 */
|
||||
[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
|
||||
/* USB Devs 18/19/22 INTA-B */
|
||||
[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x1F,0x1F,
|
||||
/* RSVD, SATA */
|
||||
[0x40] = 0x1F, 0x13
|
||||
};
|
||||
|
||||
/*
|
||||
* This table defines the index into the picr/intr_data
|
||||
* tables for each device. Any enabled device and slot
|
||||
* that uses hardware interrupts should have an entry
|
||||
* in this table to define its index into the FCH
|
||||
* PCI_INTR register 0xC00/0xC01. This index will define
|
||||
* the interrupt that it should use. Putting PIRQ_A into
|
||||
* the PIN A index for a device will tell that device to
|
||||
* use PIC IRQ 10 if it uses PIN A for its hardware INT.
|
||||
*/
|
||||
static const struct pirq_struct mainboard_pirq_data[] = {
|
||||
/* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
|
||||
{GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
|
||||
{ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */
|
||||
{NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */
|
||||
{NB_PCIE_PORT5_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* Edge: 02.5 */
|
||||
{XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */
|
||||
{SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
|
||||
{OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
|
||||
{EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
|
||||
{OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
|
||||
{EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
|
||||
{OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */
|
||||
{EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */
|
||||
{HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
|
||||
};
|
||||
|
||||
/* PIRQ Setup */
|
||||
static void pirq_setup(void)
|
||||
{
|
||||
pirq_data_ptr = mainboard_pirq_data;
|
||||
pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
|
||||
intr_data_ptr = mainboard_intr_data;
|
||||
picr_data_ptr = mainboard_picr_data;
|
||||
}
|
||||
|
||||
/**********************************************
|
||||
* enable the dedicated function in mainboard.
|
||||
**********************************************/
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
/* Initialize the PIRQ data structures for consumption */
|
||||
pirq_setup();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
if VENDOR_BAP
|
||||
|
||||
choice
|
||||
prompt "Mainboard model"
|
||||
|
||||
source "src/mainboard/bap/*/Kconfig.name"
|
||||
|
||||
endchoice
|
||||
|
||||
source "src/mainboard/bap/*/Kconfig"
|
||||
|
||||
config MAINBOARD_VENDOR
|
||||
default "BAP"
|
||||
|
||||
endif # VENDOR_BAP
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config VENDOR_BAP
|
||||
bool "BAP"
|
||||
|
|
@ -1,203 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <AGESA.h>
|
||||
#include <northbridge/amd/agesa/BiosCallOuts.h>
|
||||
#include <northbridge/amd/agesa/state_machine.h>
|
||||
#include <FchPlatform.h>
|
||||
#include <spd_bin.h>
|
||||
|
||||
#include "imc.h"
|
||||
|
||||
static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
|
||||
|
||||
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
|
||||
{
|
||||
{AGESA_DO_RESET, agesa_Reset },
|
||||
{AGESA_READ_SPD, board_ReadSpd_from_cbfs },
|
||||
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
|
||||
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
|
||||
{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
|
||||
{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
|
||||
{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
|
||||
{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
|
||||
};
|
||||
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
|
||||
|
||||
/**
|
||||
* ALC272 Verb Table
|
||||
*/
|
||||
const CODEC_ENTRY Alc272_VerbTbl[] = {
|
||||
{0x11, 0x411111F0}, // - SPDIF_OUT2
|
||||
{0x12, 0x411111F0}, // - DMIC_1/2
|
||||
{0x13, 0x411111F0}, // - DMIC_3/4
|
||||
{0x14, 0x411111F0}, // Port D - LOUT1
|
||||
{0x15, 0x01011050}, // Port A - LOUT2 Explorer 2x DAC
|
||||
{0x16, 0x411111F0}, //
|
||||
{0x17, 0x411111F0}, // Port H - MONO
|
||||
{0x18, 0x01a11840}, // Port B - MIC1
|
||||
{0x19, 0x411111F0}, // Port F - MIC2
|
||||
{0x1a, 0x01811030}, // Port C - LINE1
|
||||
{0x1b, 0x01811020}, // Port E - LINE2 Explorer 2x ADC
|
||||
{0x1d, 0x40130605}, // - PCBEEP
|
||||
{0x1e, 0x411111F0}, // - SPDIF_OUT1
|
||||
{0x21, 0x01211010}, // Port I - HPOUT
|
||||
{0xff, 0xffffffff}
|
||||
};
|
||||
|
||||
static const CODEC_TBL_LIST CodecTableList[] =
|
||||
{
|
||||
{0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]},
|
||||
{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
|
||||
};
|
||||
|
||||
#define FAN_INPUT_INTERNAL_DIODE 0
|
||||
#define FAN_INPUT_TEMP0 1
|
||||
#define FAN_INPUT_TEMP1 2
|
||||
#define FAN_INPUT_TEMP2 3
|
||||
#define FAN_INPUT_TEMP3 4
|
||||
#define FAN_INPUT_TEMP0_FILTER 5
|
||||
#define FAN_INPUT_ZERO 6
|
||||
#define FAN_INPUT_DISABLED 7
|
||||
|
||||
#define FAN_AUTOMODE (1 << 0)
|
||||
#define FAN_LINEARMODE (1 << 1)
|
||||
#define FAN_STEPMODE ~(1 << 1)
|
||||
#define FAN_POLARITY_HIGH (1 << 2)
|
||||
#define FAN_POLARITY_LOW ~(1 << 2)
|
||||
|
||||
/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
|
||||
#define FREQ_28KHZ 0x0
|
||||
#define FREQ_25KHZ 0x1
|
||||
#define FREQ_23KHZ 0x2
|
||||
#define FREQ_21KHZ 0x3
|
||||
#define FREQ_29KHZ 0x4
|
||||
#define FREQ_18KHZ 0x5
|
||||
#define FREQ_100HZ 0xF7
|
||||
#define FREQ_87HZ 0xF8
|
||||
#define FREQ_58HZ 0xF9
|
||||
#define FREQ_44HZ 0xFA
|
||||
#define FREQ_35HZ 0xFB
|
||||
#define FREQ_29HZ 0xFC
|
||||
#define FREQ_22HZ 0xFD
|
||||
#define FREQ_14HZ 0xFE
|
||||
#define FREQ_11HZ 0xFF
|
||||
|
||||
/* Hardware Monitor Fan Control
|
||||
* Hardware limitation:
|
||||
* HWM failed to read the input temperature via I2C,
|
||||
* if other software switches the I2C switch by mistake or intention.
|
||||
* We recommend using IMC to control Fans, instead of HWM.
|
||||
*/
|
||||
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
|
||||
{
|
||||
/* Enable IMC fan control, the recommended way */
|
||||
if (CONFIG(HUDSON_IMC_FWM)) {
|
||||
imc_reg_init();
|
||||
|
||||
/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
|
||||
FchParams->Hwm.HwMonitorEnable = TRUE;
|
||||
FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */
|
||||
|
||||
FchParams->Imc.ImcEnable = TRUE;
|
||||
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
|
||||
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
|
||||
|
||||
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
|
||||
|
||||
/* Thermal Zone Parameter */
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5;
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3;
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01;
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;
|
||||
|
||||
/* IMC Fan Policy temperature thresholds */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 50; /*AC0 threshold in Celsius */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 45; /*AC1 threshold in Celsius */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 40; /*AC2 threshold in Celsius */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
|
||||
|
||||
/* IMC Fan Policy PWM Settings */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 100; /* AL0 percentage */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 99; /* AL1 percentage */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 98; /* AL2 percentage */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */
|
||||
|
||||
FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;
|
||||
|
||||
/* NOTE:
|
||||
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
|
||||
* AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it.
|
||||
* So we remove it from AGESA code. Please See FchInitLateHwm.
|
||||
*/
|
||||
} else {
|
||||
/* HWM fan control, the way not recommended */
|
||||
FchParams->Imc.ImcEnable = FALSE;
|
||||
FchParams->Hwm.HwMonitorEnable = TRUE;
|
||||
FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */
|
||||
}
|
||||
}
|
||||
|
||||
void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
|
||||
{
|
||||
}
|
||||
|
||||
void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
|
||||
{
|
||||
/* Azalia Controller OEM Codec Table Pointer */
|
||||
FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
|
||||
|
||||
/* Fan Control */
|
||||
oem_fan_control(FchParams_env);
|
||||
|
||||
/* sata configuration */
|
||||
/* disable GEN2 limitation */
|
||||
FchParams_env->Sata.SataMode.SataSetMaxGen2 = FALSE;
|
||||
}
|
||||
|
||||
static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
|
||||
{
|
||||
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
|
||||
u8 index;
|
||||
|
||||
if (!ENV_RAMINIT)
|
||||
return AGESA_UNSUPPORTED;
|
||||
|
||||
if (CONFIG(BAP_E20_DDR3_1066))
|
||||
index = 1;
|
||||
else /* CONFIG_BAP_E20_DDR3_800 */
|
||||
index = 0;
|
||||
|
||||
if (info->MemChannelId > 0)
|
||||
return AGESA_UNSUPPORTED;
|
||||
if (info->SocketId != 0)
|
||||
return AGESA_UNSUPPORTED;
|
||||
if (info->DimmId != 0)
|
||||
return AGESA_UNSUPPORTED;
|
||||
|
||||
/* Read index 0, first SPD_SIZE bytes of spd.bin file. */
|
||||
if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, index) < 0)
|
||||
die("No SPD data\n");
|
||||
|
||||
return AGESA_SUCCESS;
|
||||
}
|
||||
|
|
@ -1,66 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
if BOARD_ODE_E20XX
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select CPU_AMD_AGESA_FAMILY16_KB
|
||||
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
|
||||
select SOUTHBRIDGE_AMD_AGESA_YANGTZE
|
||||
select DEFAULT_POST_ON_LPC
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_4096
|
||||
select GFXUMA
|
||||
select SUPERIO_FINTEK_F81866D
|
||||
select HAVE_SPD_IN_CBFS
|
||||
|
||||
config MAINBOARD_DIR
|
||||
default "bap/ode_e20XX"
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
default "ODE_E20XX"
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
default 0x200000
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
||||
config ONBOARD_VGA_IS_PRIMARY
|
||||
bool
|
||||
default y
|
||||
|
||||
config HUDSON_LEGACY_FREE
|
||||
bool
|
||||
default y
|
||||
|
||||
choice
|
||||
prompt "Select DDR3 clock"
|
||||
default BAP_E20_DDR3_1066
|
||||
help
|
||||
Select your preferred DDR3 clock setting.
|
||||
|
||||
Note: This option changes the total power consumption.
|
||||
|
||||
If unsure, use DDR3-1066.
|
||||
|
||||
config BAP_E20_DDR3_800
|
||||
bool "Select DDR3-800"
|
||||
|
||||
config BAP_E20_DDR3_1066
|
||||
bool "Select DDR3-1066"
|
||||
|
||||
endchoice
|
||||
|
||||
config DIMM_SPD_SIZE
|
||||
default 128
|
||||
|
||||
endif # BOARD_ODE_E20XX
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config BOARD_ODE_E20XX
|
||||
bool "ODE_e20xx"
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
bootblock-y += bootblock.c
|
||||
|
||||
romstage-y += buildOpts.c
|
||||
romstage-y += BiosCallOuts.c
|
||||
romstage-y += OemCustomize.c
|
||||
|
||||
ramstage-y += buildOpts.c
|
||||
ramstage-y += BiosCallOuts.c
|
||||
ramstage-y += OemCustomize.c
|
||||
|
||||
# Order of names in SPD_SOURCES is important!
|
||||
SPD_SOURCES = BAP_Q7_800 BAP_Q7_1066
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <AGESA.h>
|
||||
#include <PlatformMemoryConfiguration.h>
|
||||
|
||||
#include <northbridge/amd/agesa/state_machine.h>
|
||||
|
||||
|
||||
static const PCIe_PORT_DESCRIPTOR PortList[] = {
|
||||
/* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device Number 2, Function 4) */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 3),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
|
||||
HotplugBasic,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x02, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lane 1, PCI Device Number 2, Function 3) */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x03, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lane 0, PCI Device Number 2, Function 2) */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x04, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, Function 1) */
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
|
||||
HotplugBasic,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x05, 0)
|
||||
}
|
||||
};
|
||||
|
||||
static const PCIe_DDI_DESCRIPTOR DdiList[] = {
|
||||
/* eDP0 to LVDS connector*/
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
|
||||
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
|
||||
},
|
||||
/* DP1 to HDMI */
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
|
||||
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
|
||||
},
|
||||
};
|
||||
|
||||
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
|
||||
.Flags = DESCRIPTOR_TERMINATE_LIST,
|
||||
.SocketId = 0,
|
||||
.PciePortList = PortList,
|
||||
.DdiLinkList = DdiList
|
||||
};
|
||||
|
||||
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
|
||||
{
|
||||
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
|
||||
FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
|
||||
FchReset->Xhci1Enable = FALSE;
|
||||
}
|
||||
|
||||
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
|
||||
{
|
||||
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* CUSTOMER OVERRIDES MEMORY TABLE
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
|
||||
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
|
||||
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
|
||||
* use its default conservative settings.
|
||||
*/
|
||||
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
|
||||
|
||||
#define SEED_WL 0x0E
|
||||
WRITE_LEVELING_SEED(
|
||||
ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
|
||||
SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,
|
||||
SEED_WL),
|
||||
|
||||
#define SEED_A 0x12
|
||||
HW_RXEN_SEED(
|
||||
ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
|
||||
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
|
||||
SEED_A),
|
||||
|
||||
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
|
||||
NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
|
||||
MOTHER_BOARD_LAYERS(LAYERS_6),
|
||||
|
||||
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
|
||||
CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
|
||||
ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
|
||||
CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
|
||||
|
||||
PSO_END
|
||||
};
|
||||
|
||||
void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
|
||||
{
|
||||
InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
|
||||
}
|
||||
|
||||
void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
|
||||
{
|
||||
/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
|
||||
InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
|
||||
}
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* IDS Option File
|
||||
*
|
||||
* This file is used to switch on/off IDS features.
|
||||
*
|
||||
*/
|
||||
#ifndef _OPTION_IDS_H_
|
||||
#define _OPTION_IDS_H_
|
||||
|
||||
/**
|
||||
*
|
||||
* This file generates the defaults tables for the Integrated Debug Support
|
||||
* Module. The documented build options are imported from a user controlled
|
||||
* file for processing. The build options for the Integrated Debug Support
|
||||
* Module are listed below:
|
||||
*
|
||||
* IDSOPT_IDS_ENABLED
|
||||
* IDSOPT_ERROR_TRAP_ENABLED
|
||||
* IDSOPT_CONTROL_ENABLED
|
||||
* IDSOPT_TRACING_ENABLED
|
||||
* IDSOPT_PERF_ANALYSIS
|
||||
* IDSOPT_ASSERT_ENABLED
|
||||
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
|
||||
*
|
||||
**/
|
||||
|
||||
#define IDSOPT_IDS_ENABLED TRUE
|
||||
//#define IDSOPT_CONTROL_ENABLED TRUE
|
||||
//#define IDSOPT_TRACING_ENABLED TRUE
|
||||
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
|
||||
//#define IDSOPT_PERF_ANALYSIS TRUE
|
||||
#define IDSOPT_ASSERT_ENABLED TRUE
|
||||
|
||||
#endif
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Scope(\_GPE) { /* Start Scope GPE */
|
||||
|
||||
/* General event 3 */
|
||||
Method(_L03) {
|
||||
/* DBGO("\\_GPE\\_L00\n") */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Legacy PM event */
|
||||
Method(_L08) {
|
||||
/* DBGO("\\_GPE\\_L08\n") */
|
||||
}
|
||||
|
||||
/* Temp warning (TWarn) event */
|
||||
Method(_L09) {
|
||||
/* DBGO("\\_GPE\\_L09\n") */
|
||||
/* Notify (\_TZ.TZ00, 0x80) */
|
||||
}
|
||||
|
||||
/* USB controller PME# */
|
||||
Method(_L0B) {
|
||||
/* DBGO("\\_GPE\\_L0B\n") */
|
||||
Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* ExtEvent0 SCI event */
|
||||
Method(_L10) {
|
||||
/* DBGO("\\_GPE\\_L10\n") */
|
||||
}
|
||||
|
||||
/* ExtEvent1 SCI event */
|
||||
Method(_L11) {
|
||||
/* DBGO("\\_GPE\\_L11\n") */
|
||||
}
|
||||
|
||||
/* GPIO0 or GEvent8 event */
|
||||
Method(_L18) {
|
||||
/* DBGO("\\_GPE\\_L18\n") */
|
||||
Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Azalia SCI event */
|
||||
Method(_L1B) {
|
||||
/* DBGO("\\_GPE\\_L1B\n") */
|
||||
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
} /* End Scope GPE */
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
|
||||
/* AcpiGpe0Blk */
|
||||
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
|
||||
Field(GP0B, ByteAcc, NoLock, Preserve) {
|
||||
, 11,
|
||||
USBS, 1,
|
||||
}
|
||||
|
|
@ -1,171 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - F16 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
|
||||
/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
|
||||
Package(){0x0001FFFF, 0, INTB, 0 },
|
||||
Package(){0x0001FFFF, 1, INTC, 0 },
|
||||
|
||||
|
||||
/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
|
||||
/* FCH devices */
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
|
||||
/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
|
||||
/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
|
||||
Package(){0x0012FFFF, 0, INTC, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0013FFFF, 0, INTC, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0016FFFF, 0, INTC, 0 },
|
||||
Package(){0x0016FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
|
||||
Package(){0x0010FFFF, 0, INTC, 0 },
|
||||
Package(){0x0010FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 17 - SATA controller */
|
||||
Package(){0x0011FFFF, 0, INTD, 0 },
|
||||
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - F15 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
|
||||
Package(){0x0001FFFF, 0, 0, 44 },
|
||||
Package(){0x0001FFFF, 1, 0, 45 },
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridges */
|
||||
Package(){0x0002FFFF, 0, 0, 24 },
|
||||
Package(){0x0002FFFF, 1, 0, 25 },
|
||||
Package(){0x0002FFFF, 2, 0, 26 },
|
||||
Package(){0x0002FFFF, 3, 0, 27 },
|
||||
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
|
||||
/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
|
||||
Package(){0x0012FFFF, 0, 0, 18 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 17 },
|
||||
|
||||
Package(){0x0016FFFF, 0, 0, 18 },
|
||||
Package(){0x0016FFFF, 1, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
|
||||
Package(){0x0010FFFF, 0, 0, 0x12},
|
||||
Package(){0x0010FFFF, 1, 0, 0x11},
|
||||
|
||||
/* Bus 0, Dev 17 - SATA controller */
|
||||
Package(){0x0011FFFF, 0, 0, 19 },
|
||||
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS2, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
/* GFX */
|
||||
Name(PS4, Package(){
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 24 },
|
||||
Package(){0x0000FFFF, 1, 0, 25 },
|
||||
Package(){0x0000FFFF, 2, 0, 26 },
|
||||
Package(){0x0000FFFF, 3, 0, 27 },
|
||||
})
|
||||
|
||||
/* GPP 0 */
|
||||
Name(PS5, Package(){
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APS5, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 28 },
|
||||
Package(){0x0000FFFF, 1, 0, 29 },
|
||||
Package(){0x0000FFFF, 2, 0, 30 },
|
||||
Package(){0x0000FFFF, 3, 0, 31 },
|
||||
})
|
||||
|
||||
/* GPP 1 */
|
||||
Name(PS6, Package(){
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS6, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 32 },
|
||||
Package(){0x0000FFFF, 1, 0, 33 },
|
||||
Package(){0x0000FFFF, 2, 0, 34 },
|
||||
Package(){0x0000FFFF, 3, 0, 35 },
|
||||
})
|
||||
|
||||
/* GPP 2 */
|
||||
Name(PS7, Package(){
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APS7, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 36 },
|
||||
Package(){0x0000FFFF, 1, 0, 37 },
|
||||
Package(){0x0000FFFF, 2, 0, 38 },
|
||||
Package(){0x0000FFFF, 3, 0, 39 },
|
||||
})
|
||||
|
||||
/* GPP 3 */
|
||||
Name(PS8, Package(){
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS8, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 40 },
|
||||
Package(){0x0000FFFF, 1, 0, 41 },
|
||||
Package(){0x0000FFFF, 2, 0, 42 },
|
||||
Package(){0x0000FFFF, 3, 0, 43 },
|
||||
})
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
/* SPDX-License-Identifier: CC-PDDC */
|
||||
|
||||
/* Please update the license if adding licensable material. */
|
||||
|
||||
/* No SATA functionality */
|
||||
|
|
@ -1,64 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Wake status package */
|
||||
Name(WKST,Package(){Zero, Zero})
|
||||
|
||||
/*
|
||||
* \_PTS - Prepare to Sleep method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2, etc
|
||||
*
|
||||
* Exit:
|
||||
* -none-
|
||||
*
|
||||
* The _PTS control method is executed at the beginning of the sleep process
|
||||
* for S1-S5. The sleeping value is passed to the _PTS control method. This
|
||||
* control method may be executed a relatively long time before entering the
|
||||
* sleep state and the OS may abort the operation without notification to
|
||||
* the ACPI driver. This method cannot modify the configuration or power
|
||||
* state of any device in the system.
|
||||
*/
|
||||
|
||||
External(\_SB.APTS, MethodObj)
|
||||
External(\_SB.AWAK, MethodObj)
|
||||
|
||||
Method(_PTS, 1) {
|
||||
/* DBGO("\\_PTS\n") */
|
||||
/* DBGO("From S0 to S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO("\n") */
|
||||
|
||||
/* Clear wake status structure. */
|
||||
WKST [0] = 0
|
||||
WKST [1] = 0
|
||||
UPWS = 7
|
||||
\_SB.APTS(Arg0)
|
||||
} /* End Method(\_PTS) */
|
||||
|
||||
/*
|
||||
* \_WAK System Wake method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2
|
||||
*
|
||||
* Exit:
|
||||
* Return package of 2 DWords
|
||||
* Dword 1 - Status
|
||||
* 0x00000000 wake succeeded
|
||||
* 0x00000001 Wake was signaled but failed due to lack of power
|
||||
* 0x00000002 Wake was signaled but failed due to thermal condition
|
||||
* Dword 2 - Power Supply state
|
||||
* if non-zero the effective S-state the power supply entered
|
||||
*/
|
||||
Method(\_WAK, 1) {
|
||||
/* DBGO("\\_WAK\n") */
|
||||
/* DBGO("From S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO(" to S0\n") */
|
||||
USBS = 1
|
||||
|
||||
\_SB.AWAK(Arg0)
|
||||
|
||||
Return(WKST)
|
||||
} /* End Method(\_WAK) */
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* SuperIO support for Windows */
|
||||
|
||||
Device (UAR1) {
|
||||
Name (_HID, EISAID ("PNP0501"))
|
||||
Name (_UID, 1)
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
|
||||
IRQNoFlags () {4}
|
||||
})
|
||||
}
|
||||
|
||||
Device (UAR2) {
|
||||
Name (_HID, EISAID ("PNP0501"))
|
||||
Name (_UID, 2)
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
|
||||
IRQNoFlags () {3}
|
||||
})
|
||||
}
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
/* SPDX-License-Identifier: CC-PDDC */
|
||||
|
||||
/* Please update the license if adding licensable material. */
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* USB overcurrent mapping pins. */
|
||||
Name(UOM0, 0)
|
||||
Name(UOM1, 2)
|
||||
Name(UOM2, 0)
|
||||
Name(UOM3, 7)
|
||||
Name(UOM4, 2)
|
||||
Name(UOM5, 2)
|
||||
Name(UOM6, 6)
|
||||
Name(UOM7, 2)
|
||||
Name(UOM8, 6)
|
||||
Name(UOM9, 6)
|
||||
|
|
@ -1 +0,0 @@
|
|||
Category: eval
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <amdblocks/acpimmio.h>
|
||||
#include <bootblock_common.h>
|
||||
#include <superio/fintek/common/fintek.h>
|
||||
#include <superio/fintek/f81866d/f81866d.h>
|
||||
|
||||
#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
|
||||
|
||||
void bootblock_mainboard_early_init(void)
|
||||
{
|
||||
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
|
||||
pm_write8(0xea, 0x1);
|
||||
|
||||
fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
|
||||
}
|
||||
|
|
@ -1,45 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <AGESA.h>
|
||||
|
||||
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
|
||||
#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
|
||||
|
||||
//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
|
||||
//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
|
||||
//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_SRAT FALSE
|
||||
#define BLDOPT_REMOVE_WHEA FALSE
|
||||
#define BLDOPT_REMOVE_CRAT TRUE
|
||||
#define BLDOPT_REMOVE_CDIT TRUE
|
||||
|
||||
/* Build configuration values here. */
|
||||
#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0
|
||||
|
||||
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
|
||||
|
||||
#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
|
||||
#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
|
||||
#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
|
||||
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
|
||||
#define BLDCFG_ENABLE_ECC_FEATURE TRUE
|
||||
#define BLDCFG_ECC_SYNC_FLOOD TRUE
|
||||
#define BLDCFG_IOMMU_SUPPORT FALSE
|
||||
|
||||
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
|
||||
|
||||
/* Include the files that instantiate the configuration definitions. */
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuFamRegisters.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "AdvancedApi.h"
|
||||
#include "heapManager.h"
|
||||
#include "CreateStruct.h"
|
||||
#include "cpuFeatures.h"
|
||||
#include "Table.h"
|
||||
#include "cpuEarlyInit.h"
|
||||
#include "cpuLateInit.h"
|
||||
#include "GnbInterface.h"
|
||||
|
||||
#include <PlatformInstall.h>
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
#*****************************************************************************
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#*****************************************************************************
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
444 1 e 1 nmi
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
|
@ -1,103 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip northbridge/amd/agesa/family16kb/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/agesa/family16kb
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x1410 inherit
|
||||
chip northbridge/amd/agesa/family16kb
|
||||
device pci 0.0 on end # Root Complex
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9835
|
||||
device pci 1.1 on end # Internal Multimedia
|
||||
device pci 2.0 on end # PCIe Host Bridge
|
||||
device pci 2.1 on end # x4 PCIe Slot
|
||||
device pci 2.2 on end # PCIe Q7 Realtek GBit LAN
|
||||
device pci 2.3 on end # PCIe CB Realtek GBit LAN
|
||||
device pci 2.4 on end # x2 PCIe Microsemi FPGA
|
||||
end #chip northbridge/amd/agesa/family16kb
|
||||
|
||||
chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
|
||||
device pci 10.0 on end # XHCI HC0
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on end # SM
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on # LPC 0x439d
|
||||
chip superio/fintek/f81866d
|
||||
register "hwm_amd_tsi_addr" = "0x98" # Set to AMD
|
||||
register "hwm_amd_tsi_control" = "0x02" # Set to AMD
|
||||
register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM
|
||||
register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode
|
||||
register "hwm_fan3_control" = "0x00" # Fan control 23kHz
|
||||
register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz
|
||||
register "hwm_fan2_bound1" = "0x3C" # 60°C
|
||||
register "hwm_fan2_bound2" = "0x32" # 50°C
|
||||
register "hwm_fan2_bound3" = "0x28" # 40°C
|
||||
register "hwm_fan2_bound4" = "0x1E" # 30°C
|
||||
register "hwm_fan2_seg1_speed" = "0xFF" # 100%
|
||||
register "hwm_fan2_seg2_speed" = "0xD9" # 85%
|
||||
register "hwm_fan2_seg3_speed" = "0xB2" # 70%
|
||||
register "hwm_fan2_seg4_speed" = "0x99" # 60%
|
||||
register "hwm_fan2_seg5_speed" = "0x80" # 50%
|
||||
register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor
|
||||
device pnp 4e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 4e.3 off end # Parallel Port
|
||||
device pnp 4e.4 on # Hardware Monitor
|
||||
io 0x60 = 0x295
|
||||
irq 0x70 = 0
|
||||
end
|
||||
device pnp 4e.5 off # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 4e.6 off end # GPIO
|
||||
device pnp 4e.7 on end # WDT
|
||||
device pnp 4e.a off end # PME
|
||||
device pnp 4e.10 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 4e.11 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 4e.12 on # COM3
|
||||
io 0x60 = 0x3e8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 4e.13 on # COM4
|
||||
io 0x60 = 0x2e8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 4e.14 off # COM5
|
||||
end
|
||||
device pnp 4e.15 off # COM6
|
||||
end
|
||||
end # f81866d
|
||||
end #LPC
|
||||
device pci 14.7 on end # SD
|
||||
end #chip southbridge/amd/agesa/hudson
|
||||
|
||||
chip northbridge/amd/agesa/family16kb
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 18.5 on end
|
||||
end
|
||||
|
||||
end #domain
|
||||
end #northbridge/amd/agesa/family16kb/root_complex
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* DefinitionBlock Statement */
|
||||
#include <acpi/acpi.h>
|
||||
DefinitionBlock (
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x00010001 /* OEM Revision */
|
||||
)
|
||||
{ /* Start of ASL file */
|
||||
#include <acpi/dsdt_top.asl>
|
||||
|
||||
/* Globals for the platform */
|
||||
#include "acpi/mainboard.asl"
|
||||
|
||||
/* Describe the USB Overcurrent pins */
|
||||
#include "acpi/usb_oc.asl"
|
||||
|
||||
/* PCI IRQ mapping for the Southbridge */
|
||||
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
|
||||
|
||||
/* Describe the processor tree (\_SB) */
|
||||
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
|
||||
|
||||
/* Contains the supported sleep states for this chipset */
|
||||
#include <southbridge/amd/common/acpi/sleepstates.asl>
|
||||
|
||||
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
|
||||
#include "acpi/sleep.asl"
|
||||
|
||||
/* System Bus */
|
||||
Scope(\_SB) { /* Start \_SB scope */
|
||||
/* global utility methods expected within the \_SB scope */
|
||||
#include <arch/x86/acpi/globutil.asl>
|
||||
|
||||
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
|
||||
#include "acpi/routing.asl"
|
||||
|
||||
Device(PWRB) {
|
||||
Name(_HID, EISAID("PNP0C0C"))
|
||||
Name(_UID, 0xAA)
|
||||
Name(_PRW, Package () {3, 0x04})
|
||||
Name(_STA, 0x0B)
|
||||
}
|
||||
|
||||
Device(PCI0) {
|
||||
/* Describe the AMD Northbridge */
|
||||
#include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>
|
||||
|
||||
/* Describe the AMD Fusion Controller Hub Southbridge */
|
||||
#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
|
||||
}
|
||||
|
||||
/* Describe PCI INT[A-H] for the Southbridge */
|
||||
#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
|
||||
|
||||
} /* End \_SB scope */
|
||||
|
||||
/* Describe SMBUS for the Southbridge */
|
||||
#include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
|
||||
|
||||
/* Define the General Purpose Events for the platform */
|
||||
#include "acpi/gpe.asl"
|
||||
|
||||
/* Define the Thermal zones and methods for the platform */
|
||||
#include "acpi/thermal.asl"
|
||||
}
|
||||
/* End of ASL file */
|
||||
|
|
@ -1,88 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <commonlib/bsd/helpers.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr = ALIGN_UP(addr, 16);
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = 0;
|
||||
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1002;
|
||||
pirq->rtr_device = 0x4384;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "%s done.\n", __func__);
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
|
|
@ -1,101 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/device.h>
|
||||
|
||||
#include <southbridge/amd/agesa/hudson/pci_devs.h>
|
||||
#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <northbridge/amd/agesa/family16kb/pci_devs.h>
|
||||
|
||||
/***********************************************************
|
||||
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
|
||||
* This table is responsible for physically routing the PIC and
|
||||
* IOAPIC IRQs to the different PCI devices on the system. It
|
||||
* is read and written via registers 0xC00/0xC01 as an
|
||||
* Index/Data pair. These values are chipset and mainboard
|
||||
* dependent and should be updated accordingly.
|
||||
*
|
||||
* These values are used by the PCI configuration space,
|
||||
* MP Tables. TODO: Make ACPI use these values too.
|
||||
*/
|
||||
static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
|
||||
/* INTA# - INTH# */
|
||||
[0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
|
||||
/* Misc-nil,0,1,2, INT from Serial irq */
|
||||
[0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
|
||||
/* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
|
||||
[0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
|
||||
/* IMC INT0 - 5 */
|
||||
[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
|
||||
/* USB Devs 18/19/22 INTA-C */
|
||||
[0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
|
||||
/* SATA */
|
||||
[0x41] = 0x0F,
|
||||
};
|
||||
|
||||
static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
|
||||
/* INTA# - INTH# */
|
||||
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
|
||||
/* Misc-nil,0,1,2, INT from Serial irq */
|
||||
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
|
||||
/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
|
||||
[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,
|
||||
/* IMC INT0 - 5 */
|
||||
[0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,
|
||||
/* USB Devs 18/19/20/22 INTA-C */
|
||||
[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
|
||||
/* SATA */
|
||||
[0x41] = 0x13
|
||||
};
|
||||
|
||||
/*
|
||||
* This table defines the index into the picr/intr_data
|
||||
* tables for each device. Any enabled device and slot
|
||||
* that uses hardware interrupts should have an entry
|
||||
* in this table to define its index into the FCH
|
||||
* PCI_INTR register 0xC00/0xC01. This index will define
|
||||
* the interrupt that it should use. Putting PIRQ_A into
|
||||
* the PIN A index for a device will tell that device to
|
||||
* use PIC IRQ 10 if it uses PIN A for its hardware INT.
|
||||
*/
|
||||
static const struct pirq_struct mainboard_pirq_data[] = {
|
||||
/* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
|
||||
{GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
|
||||
{ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */
|
||||
{NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */
|
||||
{NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */
|
||||
{NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */
|
||||
{NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* Edge: 02.4 */
|
||||
{NB_PCIE_PORT5_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_G, PIRQ_H}}, /* Edge: 02.5 */
|
||||
{XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */
|
||||
{SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
|
||||
{OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
|
||||
{EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
|
||||
{OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
|
||||
{EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
|
||||
{SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
|
||||
{HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
|
||||
{SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */
|
||||
};
|
||||
|
||||
/* PIRQ Setup */
|
||||
static void pirq_setup(void)
|
||||
{
|
||||
pirq_data_ptr = mainboard_pirq_data;
|
||||
pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
|
||||
intr_data_ptr = mainboard_intr_data;
|
||||
picr_data_ptr = mainboard_picr_data;
|
||||
}
|
||||
|
||||
/**********************************************
|
||||
* enable the dedicated function in mainboard.
|
||||
**********************************************/
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
/* Initialize the PIRQ data structures for consumption */
|
||||
pirq_setup();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -1,217 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
|
||||
# BAP ODE E20XX has 2GB RAM soldered down on the Q7
|
||||
# Memory setting for DDR-1066
|
||||
|
||||
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
|
||||
# bits[3:0]: 1 = 128 SPD Bytes Used
|
||||
# bits[6:4]: 1 = 256 SPD Bytes Total
|
||||
# bit7 : 0 = CRC covers bytes 0 ~ 125
|
||||
11
|
||||
|
||||
# 1 SPD Revision -
|
||||
# 0x12 = Revision 1.2
|
||||
12
|
||||
|
||||
# 2 Key Byte / DRAM Device Type
|
||||
# bits[7:0]: 0x0b = DDR3 SDRAM
|
||||
0B
|
||||
|
||||
# 3 Key Byte / Module Type
|
||||
# bits[3:0]: 3 = SO-DIMM
|
||||
# bits[7:4]: reserved
|
||||
03
|
||||
|
||||
# 4 SDRAM CHIP Density and Banks
|
||||
# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
|
||||
# bits[6:4]: 0 = 3 (8 banks)
|
||||
# bit7 : reserved
|
||||
04
|
||||
|
||||
# 5 SDRAM Addressing
|
||||
# bits[2:0]: 1 = 10 Column Address Bits
|
||||
# bits[5:3]: 3 = 15 Row Address Bits
|
||||
# bits[7:6]: reserved
|
||||
19
|
||||
|
||||
# 6 Module Nominal Voltage, VDD
|
||||
# bit0 : 0 = 1.5 V operable
|
||||
# bit1 : 0 = NOT 1.35 V operable
|
||||
# bit2 : 0 = NOT 1.25 V operable
|
||||
# bits[7:3]: reserved
|
||||
00
|
||||
|
||||
# 7 Module Organization
|
||||
# bits[2:0]: 2 = 16 bits
|
||||
# bits[5:3]: 0 = 1 Rank
|
||||
# bits[7:6]: reserved
|
||||
02
|
||||
|
||||
# 8 Module Memory Bus Width
|
||||
# bits[2:0]: 3 = Primary bus width is 64 bits
|
||||
# bits[4:3]: 1 = 1 bit (bus width extension ECC)
|
||||
# bits[7:5]: reserved
|
||||
0B
|
||||
|
||||
# 9 Fine Timebase (FTB) Dividend / Divisor
|
||||
# bits[3:0]: 0x01 divisor
|
||||
# bits[7:4]: 0x01 dividend
|
||||
# 1/1 = 1ps
|
||||
11
|
||||
|
||||
# 10 Medium Timebase (MTB) Dividend
|
||||
# 11 Medium Timebase (MTB) Divisor
|
||||
# 1 / 8 = .125 ns - used for DDR3
|
||||
01 08
|
||||
|
||||
# 12 SDRAM Minimum Cycle Time (tCKmin)
|
||||
# 0x0F = tCKmin of 1.875 ns = DDR3-1066 (533 MHz clock)
|
||||
0F
|
||||
|
||||
# 13 Reserved
|
||||
00
|
||||
|
||||
# 14 CAS Latencies Supported, Least Significant Byte
|
||||
# 15 CAS Latencies Supported, Most Significant Byte
|
||||
# Cas Latencies of 8 - 5 are supported
|
||||
1E 00
|
||||
|
||||
# 16 Minimum CAS Latency Time (tAAmin)
|
||||
# 0x69 = 13.125ns - DDR3-1066F
|
||||
69
|
||||
|
||||
# 17 Minimum Write Recovery Time (tWRmin)
|
||||
# 0x78 = tWR of 15ns - All DDR3 speed grades
|
||||
78
|
||||
|
||||
# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
|
||||
# 0x69 = 13.125ns - DDR3-1066F
|
||||
69
|
||||
|
||||
# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
|
||||
# 0x3C = 7.5ns
|
||||
3C
|
||||
|
||||
# 20 Minimum Row Precharge Delay Time (tRPmin)
|
||||
# 0x69 = 13.125ns - DDR3-1066F
|
||||
69
|
||||
|
||||
# 21 Upper Nibbles for tRAS and tRC
|
||||
# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
|
||||
# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
|
||||
11
|
||||
|
||||
# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
|
||||
# 0x12C = 37.5ns - DDR3-1066 (see byte 21)
|
||||
2C
|
||||
|
||||
# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
|
||||
# 0x195 = 50.625ns - DDR3-1066F (see byte 21)
|
||||
95
|
||||
|
||||
# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
|
||||
# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
|
||||
# 0x500 = 160ns - for 2 Gigabit chips
|
||||
80 07
|
||||
|
||||
# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
|
||||
# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
|
||||
3C
|
||||
|
||||
# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
|
||||
# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
|
||||
3C
|
||||
|
||||
# 28 Upper Nibble for tFAWmin
|
||||
# 29 Minimum Four Activate Window Delay Time (tFAWmin)
|
||||
# 0x0190 = 50ns - DDR3-1066, 2 KB page size
|
||||
01 90
|
||||
|
||||
# 30 SDRAM Optional Feature
|
||||
# bit0 : 1= RZQ/6 supported
|
||||
# bit1 : 1 = RZQ/7 supported
|
||||
# bits[6:2]: reserved
|
||||
# bit7 : 0 = DLL Off mode supported
|
||||
03
|
||||
|
||||
# 31 SDRAM Thermal and Refresh Options
|
||||
# bit0 : 0 = Temp up to 95c supported
|
||||
# bit1 : 0 = 85-95c uses 2x refresh rate
|
||||
# bit2 : 1 = Auto Self Refresh supported
|
||||
# bit3 : 0 = no on die thermal sensor
|
||||
# bits[6:4]: reserved
|
||||
# bit7 : 0 = partial self refresh supported
|
||||
04
|
||||
|
||||
# 32 Module Thermal Sensor
|
||||
# 0 = Thermal sensor not incorporated onto this assembly
|
||||
00
|
||||
|
||||
# 33 SDRAM Device Type
|
||||
# bits[1:0]: 0 = Signal Loading not specified
|
||||
# bits[3:2]: reserved
|
||||
# bits[6:4]: 0 = Die count not specified
|
||||
# bit7 : 0 = Standard Monolithic DRAM Device
|
||||
00
|
||||
|
||||
# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
|
||||
# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
|
||||
# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
|
||||
# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
|
||||
# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
|
||||
00 00 00 00 00
|
||||
|
||||
# 39 - 59 (reserved)
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00
|
||||
|
||||
# 60 Raw Card Extension, Module Nominal Height
|
||||
# bits[4:0]: 0 = <= 15mm tall
|
||||
# bits[7:5]: 0 = raw card revision 0-3
|
||||
00
|
||||
|
||||
# 61 Module Maximum Thickness
|
||||
# bits[3:0]: 0 = thickness front <= 1mm
|
||||
# bits[7:4]: 0 = thinkness back <= 1mm
|
||||
00
|
||||
|
||||
# 62 Reference Raw Card Used
|
||||
# bits[4:0]: 0 = Reference Raw card A used
|
||||
# bits[6:5]: 0 = revision 0
|
||||
# bit7 : 0 = Reference raw cards A through AL
|
||||
00
|
||||
|
||||
# 63 Address Mapping from Edge Connector to DRAM
|
||||
# bit0 : 0 = standard mapping (not mirrored)
|
||||
# bits[7:1]: reserved
|
||||
00
|
||||
|
||||
# 64 - 116 (reserved)
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00
|
||||
|
||||
# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
|
||||
# 0x80AD = Hynix
|
||||
80 AD
|
||||
|
||||
# 119 Module ID: Module Manufacturing Location - oem specified
|
||||
# 120 Module ID: Module Manufacture Year in BCD
|
||||
# 0x00 = 2000
|
||||
00 00
|
||||
|
||||
# 121 Module ID: Module Manufacture week
|
||||
# 0x00 = 0th week
|
||||
00
|
||||
|
||||
# 122 - 125: Module Serial Number
|
||||
00 00 00 00
|
||||
|
||||
# 126 - 127: Cyclical Redundancy Code
|
||||
E9 40
|
||||
|
|
@ -1,217 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
|
||||
# BAP ODE E20XX has 2GB RAM soldered down on the Q7
|
||||
# Memory setting for DDR-800
|
||||
|
||||
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
|
||||
# bits[3:0]: 1 = 128 SPD Bytes Used
|
||||
# bits[6:4]: 1 = 256 SPD Bytes Total
|
||||
# bit7 : 0 = CRC covers bytes 0 ~ 125
|
||||
11
|
||||
|
||||
# 1 SPD Revision -
|
||||
# 0x11 = Revision 1.1
|
||||
11
|
||||
|
||||
# 2 Key Byte / DRAM Device Type
|
||||
# bits[7:0]: 0x0b = DDR3 SDRAM
|
||||
0B
|
||||
|
||||
# 3 Key Byte / Module Type
|
||||
# bits[3:0]: 3 = SO-DIMM
|
||||
# bits[7:4]: reserved
|
||||
03
|
||||
|
||||
# 4 SDRAM CHIP Density and Banks
|
||||
# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
|
||||
# bits[6:4]: 0 = 3 (8 banks)
|
||||
# bit7 : reserved
|
||||
04
|
||||
|
||||
# 5 SDRAM Addressing
|
||||
# bits[2:0]: 1 = 10 Column Address Bits
|
||||
# bits[5:3]: 3 = 15 Row Address Bits
|
||||
# bits[7:6]: reserved
|
||||
19
|
||||
|
||||
# 6 Module Nominal Voltage, VDD
|
||||
# bit0 : 0 = 1.5 V operable
|
||||
# bit1 : 0 = NOT 1.35 V operable
|
||||
# bit2 : 0 = NOT 1.25 V operable
|
||||
# bits[7:3]: reserved
|
||||
00
|
||||
|
||||
# 7 Module Organization
|
||||
# bits[2:0]: 2 = 16 bits
|
||||
# bits[5:3]: 0 = 1 Rank
|
||||
# bits[7:6]: reserved
|
||||
02
|
||||
|
||||
# 8 Module Memory Bus Width
|
||||
# bits[2:0]: 3 = Primary bus width is 64 bits
|
||||
# bits[4:3]: 1 = 1 bit (bus width extension ECC)
|
||||
# bits[7:5]: reserved
|
||||
0B
|
||||
|
||||
# 9 Fine Timebase (FTB) Dividend / Divisor
|
||||
# bits[3:0]: 0x01 divisor
|
||||
# bits[7:4]: 0x01 dividend
|
||||
# 1/1 = 1ps
|
||||
11
|
||||
|
||||
# 10 Medium Timebase (MTB) Dividend
|
||||
# 11 Medium Timebase (MTB) Divisor
|
||||
# 1 / 8 = .125 ns - used for DDR3
|
||||
01 08
|
||||
|
||||
# 12 SDRAM Minimum Cycle Time (tCKmin)
|
||||
# 0x14 = tCKmin of 2.5 ns = DDR3-800 (400 MHz clock)
|
||||
14
|
||||
|
||||
# 13 Reserved
|
||||
00
|
||||
|
||||
# 14 CAS Latencies Supported, Least Significant Byte
|
||||
# 15 CAS Latencies Supported, Most Significant Byte
|
||||
# CAS Latencies of 6 - 5 are supported
|
||||
06 00
|
||||
|
||||
# 16 Minimum CAS Latency Time (tAAmin)
|
||||
# 0x78 = 15ns - DDR3-800E
|
||||
78
|
||||
|
||||
# 17 Minimum Write Recovery Time (tWRmin)
|
||||
# 0x78 = tWR of 15ns - All DDR3 speed grades
|
||||
78
|
||||
|
||||
# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
|
||||
# 0x6E = 15ns - DDR3-800E
|
||||
78
|
||||
|
||||
# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
|
||||
# 0x3C = 7.5ns
|
||||
3C
|
||||
|
||||
# 20 Minimum Row Precharge Delay Time (tRPmin)
|
||||
# 0x6E = 15ns - DDR3-800E
|
||||
78
|
||||
|
||||
# 21 Upper Nibbles for tRAS and tRC
|
||||
# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
|
||||
# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
|
||||
11
|
||||
|
||||
# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
|
||||
# 0x12C = 37.5ns - DDR3-800E (see byte 21)
|
||||
2C
|
||||
|
||||
# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
|
||||
# 0x1A4 = 52.5ns - DDR3-800E (see byte 21)
|
||||
A4
|
||||
|
||||
# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
|
||||
# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
|
||||
# 0x780 = 208ns - for 4 Gigabit chips
|
||||
80 07
|
||||
|
||||
# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
|
||||
# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
|
||||
3C
|
||||
|
||||
# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
|
||||
# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
|
||||
3C
|
||||
|
||||
# 28 Upper Nibble for tFAWmin
|
||||
# 29 Minimum Four Activate Window Delay Time (tFAWmin)
|
||||
# 0x0190 = 50ns - DDR3-800, 2 KB page size
|
||||
01 90
|
||||
|
||||
# 30 SDRAM Optional Feature
|
||||
# bit0 : 1= RZQ/6 supported
|
||||
# bit1 : 1 = RZQ/7 supported
|
||||
# bits[6:2]: reserved
|
||||
# bit7 : 0 = DLL Off mode supported
|
||||
03
|
||||
|
||||
# 31 SDRAM Thermal and Refresh Options
|
||||
# bit0 : 0 = Temp up to 95c supported
|
||||
# bit1 : 0 = 85-95c uses 2x refresh rate
|
||||
# bit2 : 1 = Auto Self Refresh supported
|
||||
# bit3 : 0 = no on die thermal sensor
|
||||
# bits[6:4]: reserved
|
||||
# bit7 : 0 = partial self refresh supported
|
||||
04
|
||||
|
||||
# 32 Module Thermal Sensor
|
||||
# 0 = Thermal sensor not incorporated onto this assembly
|
||||
00
|
||||
|
||||
# 33 SDRAM Device Type
|
||||
# bits[1:0]: 0 = Signal Loading not specified
|
||||
# bits[3:2]: reserved
|
||||
# bits[6:4]: 0 = Die count not specified
|
||||
# bit7 : 0 = Standard Monolithic DRAM Device
|
||||
00
|
||||
|
||||
# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
|
||||
# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
|
||||
# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
|
||||
# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
|
||||
# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
|
||||
00 00 00 00 00
|
||||
|
||||
# 39 - 59 (reserved)
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00
|
||||
|
||||
# 60 Raw Card Extension, Module Nominal Height
|
||||
# bits[4:0]: 0 = <= 15mm tall
|
||||
# bits[7:5]: 0 = raw card revision 0-3
|
||||
00
|
||||
|
||||
# 61 Module Maximum Thickness
|
||||
# bits[3:0]: 0 = thickness front <= 1mm
|
||||
# bits[7:4]: 0 = thinkness back <= 1mm
|
||||
00
|
||||
|
||||
# 62 Reference Raw Card Used
|
||||
# bits[4:0]: 0 = Reference Raw card A used
|
||||
# bits[6:5]: 0 = revision 0
|
||||
# bit7 : 0 = Reference raw cards A through AL
|
||||
00
|
||||
|
||||
# 63 Address Mapping from Edge Connector to DRAM
|
||||
# bit0 : 0 = standard mapping (not mirrored)
|
||||
# bits[7:1]: reserved
|
||||
00
|
||||
|
||||
# 64 - 116 (reserved)
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00
|
||||
|
||||
# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
|
||||
# 0x80AD = Hynix
|
||||
80 AD
|
||||
|
||||
# 119 Module ID: Module Manufacturing Location - oem specified
|
||||
# 120 Module ID: Module Manufacture Year in BCD
|
||||
# 0x00 = 2000
|
||||
00 00
|
||||
|
||||
# 121 Module ID: Module Manufacture week
|
||||
# 0x00 = 0th week
|
||||
00
|
||||
|
||||
# 122 - 125: Module Serial Number
|
||||
00 00 00 00
|
||||
|
||||
# 126 - 127: Cyclical Redundancy Code
|
||||
48 91
|
||||
|
|
@ -1,170 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <AGESA.h>
|
||||
#include <northbridge/amd/agesa/BiosCallOuts.h>
|
||||
#include <northbridge/amd/agesa/state_machine.h>
|
||||
#include <FchPlatform.h>
|
||||
|
||||
#include "imc.h"
|
||||
|
||||
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
|
||||
{
|
||||
{AGESA_DO_RESET, agesa_Reset },
|
||||
{AGESA_READ_SPD, agesa_ReadSpd },
|
||||
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
|
||||
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
|
||||
{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
|
||||
{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
|
||||
{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
|
||||
{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
|
||||
};
|
||||
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
|
||||
|
||||
/**
|
||||
* AMD Olivehill Platform ALC272 Verb Table
|
||||
*/
|
||||
static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = {
|
||||
{0x11, 0x411111F0}, // - SPDIF_OUT2
|
||||
{0x12, 0x411111F0}, // - DMIC_1/2
|
||||
{0x13, 0x411111F0}, // - DMIC_3/4
|
||||
{0x14, 0x411111F0}, // Port D - LOUT1
|
||||
{0x15, 0x411111F0}, // Port A - LOUT2
|
||||
{0x16, 0x411111F0}, //
|
||||
{0x17, 0x411111F0}, // Port H - MONO
|
||||
{0x18, 0x01a19840}, // Port B - MIC1
|
||||
{0x19, 0x411111F0}, // Port F - MIC2
|
||||
{0x1a, 0x01813030}, // Port C - LINE1
|
||||
{0x1b, 0x411111F0}, // Port E - LINE2
|
||||
{0x1d, 0x40130605}, // - PCBEEP
|
||||
{0x1e, 0x01441120}, // - SPDIF_OUT1
|
||||
{0x21, 0x01214010}, // Port I - HPOUT
|
||||
{0xff, 0xffffffff}
|
||||
};
|
||||
|
||||
static const CODEC_TBL_LIST OlivehillCodecTableList[] =
|
||||
{
|
||||
{0x10ec0272, (CODEC_ENTRY*)&Olivehill_Alc272_VerbTbl[0]},
|
||||
{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
|
||||
};
|
||||
|
||||
#define FAN_INPUT_INTERNAL_DIODE 0
|
||||
#define FAN_INPUT_TEMP0 1
|
||||
#define FAN_INPUT_TEMP1 2
|
||||
#define FAN_INPUT_TEMP2 3
|
||||
#define FAN_INPUT_TEMP3 4
|
||||
#define FAN_INPUT_TEMP0_FILTER 5
|
||||
#define FAN_INPUT_ZERO 6
|
||||
#define FAN_INPUT_DISABLED 7
|
||||
|
||||
#define FAN_AUTOMODE (1 << 0)
|
||||
#define FAN_LINEARMODE (1 << 1)
|
||||
#define FAN_STEPMODE ~(1 << 1)
|
||||
#define FAN_POLARITY_HIGH (1 << 2)
|
||||
#define FAN_POLARITY_LOW ~(1 << 2)
|
||||
|
||||
/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
|
||||
#define FREQ_28KHZ 0x0
|
||||
#define FREQ_25KHZ 0x1
|
||||
#define FREQ_23KHZ 0x2
|
||||
#define FREQ_21KHZ 0x3
|
||||
#define FREQ_29KHZ 0x4
|
||||
#define FREQ_18KHZ 0x5
|
||||
#define FREQ_100HZ 0xF7
|
||||
#define FREQ_87HZ 0xF8
|
||||
#define FREQ_58HZ 0xF9
|
||||
#define FREQ_44HZ 0xFA
|
||||
#define FREQ_35HZ 0xFB
|
||||
#define FREQ_29HZ 0xFC
|
||||
#define FREQ_22HZ 0xFD
|
||||
#define FREQ_14HZ 0xFE
|
||||
#define FREQ_11HZ 0xFF
|
||||
|
||||
/* Hardware Monitor Fan Control
|
||||
* Hardware limitation:
|
||||
* HWM failed to read the input temperature via I2C,
|
||||
* if other software switches the I2C switch by mistake or intention.
|
||||
* We recommend using IMC to control Fans, instead of HWM.
|
||||
*/
|
||||
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
|
||||
{
|
||||
/* Enable IMC fan control, the recommended way */
|
||||
if (CONFIG(HUDSON_IMC_FWM)) {
|
||||
imc_reg_init();
|
||||
|
||||
/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
|
||||
FchParams->Hwm.HwMonitorEnable = TRUE;
|
||||
FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */
|
||||
|
||||
FchParams->Imc.ImcEnable = TRUE;
|
||||
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
|
||||
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
|
||||
|
||||
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
|
||||
|
||||
/* Thermal Zone Parameter */
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5;
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3;
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01;
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */
|
||||
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;
|
||||
|
||||
/* IMC Fan Policy temperature thresholds */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */
|
||||
FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
|
||||
|
||||
/* IMC Fan Policy PWM Settings */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */
|
||||
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */
|
||||
|
||||
FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;
|
||||
|
||||
/* NOTE:
|
||||
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
|
||||
* AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it.
|
||||
* So we remove it from AGESA code. Please See FchInitLateHwm.
|
||||
*/
|
||||
} else {
|
||||
/* HWM fan control, the way not recommended */
|
||||
FchParams->Imc.ImcEnable = FALSE;
|
||||
FchParams->Hwm.HwMonitorEnable = TRUE;
|
||||
FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */
|
||||
}
|
||||
}
|
||||
|
||||
void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
|
||||
{
|
||||
FchParams_reset->Mode = FCH_SPI_MODE_NORMAL;
|
||||
FchParams_reset->QeEnabled = FALSE;
|
||||
}
|
||||
|
||||
void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
|
||||
{
|
||||
/* Azalia Controller OEM Codec Table Pointer */
|
||||
FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]);
|
||||
|
||||
/* Fan Control */
|
||||
oem_fan_control(FchParams_env);
|
||||
}
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
if BOARD_BIOSTAR_A68N5200
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select CPU_AMD_AGESA_FAMILY16_KB
|
||||
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
|
||||
select SOUTHBRIDGE_AMD_AGESA_YANGTZE
|
||||
select SUPERIO_ITE_IT8728F
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_4096
|
||||
select GFXUMA
|
||||
|
||||
config MAINBOARD_DIR
|
||||
default "biostar/a68n_5200"
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
default "A68N5200"
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
default 0x200000
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
||||
config ONBOARD_VGA_IS_PRIMARY
|
||||
bool
|
||||
default y
|
||||
|
||||
config HUDSON_LEGACY_FREE
|
||||
bool
|
||||
default n
|
||||
|
||||
endif # BOARD_BIOSTAR_A68N5200
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config BOARD_BIOSTAR_A68N5200
|
||||
bool "A68N-5200"
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
bootblock-y += bootblock.c
|
||||
|
||||
romstage-y += buildOpts.c
|
||||
romstage-y += BiosCallOuts.c
|
||||
romstage-y += OemCustomize.c
|
||||
|
||||
ramstage-y += buildOpts.c
|
||||
ramstage-y += BiosCallOuts.c
|
||||
ramstage-y += OemCustomize.c
|
||||
|
|
@ -1,139 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <AGESA.h>
|
||||
#include <PlatformMemoryConfiguration.h>
|
||||
|
||||
#include <northbridge/amd/agesa/state_machine.h>
|
||||
|
||||
static const PCIe_PORT_DESCRIPTOR PortList[] = {
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x01, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x02, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x03, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x04, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x05, 0)
|
||||
}
|
||||
};
|
||||
|
||||
static const PCIe_DDI_DESCRIPTOR DdiList[] = {
|
||||
/* DP0 to HDMI0/DP */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
|
||||
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
|
||||
},
|
||||
/* DP1 to FCH */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
|
||||
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
|
||||
},
|
||||
/* DP2 to HDMI1/DP */
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
|
||||
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3)
|
||||
},
|
||||
};
|
||||
|
||||
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
|
||||
.Flags = DESCRIPTOR_TERMINATE_LIST,
|
||||
.SocketId = 0,
|
||||
.PciePortList = PortList,
|
||||
.DdiLinkList = DdiList
|
||||
};
|
||||
|
||||
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
|
||||
{
|
||||
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
|
||||
FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
|
||||
FchReset->Xhci1Enable = FALSE;
|
||||
}
|
||||
|
||||
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
|
||||
{
|
||||
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* CUSTOMER OVERRIDES MEMORY TABLE
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
|
||||
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
|
||||
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
|
||||
* use its default conservative settings.
|
||||
*/
|
||||
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
|
||||
#define SEED_A 0x12
|
||||
HW_RXEN_SEED(
|
||||
ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
|
||||
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
|
||||
SEED_A),
|
||||
|
||||
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
|
||||
NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
|
||||
MOTHER_BOARD_LAYERS(LAYERS_4),
|
||||
|
||||
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
|
||||
CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
|
||||
ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
|
||||
CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
|
||||
|
||||
PSO_END
|
||||
};
|
||||
|
||||
void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
|
||||
{
|
||||
InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
|
||||
}
|
||||
|
||||
void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
|
||||
{
|
||||
/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
|
||||
InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
|
||||
}
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* IDS Option File
|
||||
*
|
||||
* This file is used to switch on/off IDS features.
|
||||
*
|
||||
*/
|
||||
#ifndef _OPTION_IDS_H_
|
||||
#define _OPTION_IDS_H_
|
||||
|
||||
/**
|
||||
*
|
||||
* This file generates the defaults tables for the Integrated Debug Support
|
||||
* Module. The documented build options are imported from a user controlled
|
||||
* file for processing. The build options for the Integrated Debug Support
|
||||
* Module are listed below:
|
||||
*
|
||||
* IDSOPT_IDS_ENABLED
|
||||
* IDSOPT_ERROR_TRAP_ENABLED
|
||||
* IDSOPT_CONTROL_ENABLED
|
||||
* IDSOPT_TRACING_ENABLED
|
||||
* IDSOPT_PERF_ANALYSIS
|
||||
* IDSOPT_ASSERT_ENABLED
|
||||
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
|
||||
*
|
||||
**/
|
||||
|
||||
#define IDSOPT_IDS_ENABLED TRUE
|
||||
//#define IDSOPT_CONTROL_ENABLED TRUE
|
||||
//#define IDSOPT_TRACING_ENABLED TRUE
|
||||
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
|
||||
//#define IDSOPT_PERF_ANALYSIS TRUE
|
||||
#define IDSOPT_ASSERT_ENABLED TRUE
|
||||
|
||||
#endif
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
//BTDC Due to IMC Fan, ACPI control codes
|
||||
OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
|
||||
Field(IMIO , ByteAcc, NoLock, Preserve) {
|
||||
IMCX,8,
|
||||
IMCA,8
|
||||
}
|
||||
|
||||
IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
|
||||
Offset(0x80),
|
||||
MSTI, 8,
|
||||
MITS, 8,
|
||||
MRG0, 8,
|
||||
MRG1, 8,
|
||||
MRG2, 8,
|
||||
MRG3, 8,
|
||||
}
|
||||
|
||||
Method(WACK, 0)
|
||||
{
|
||||
Local0 = 0
|
||||
While (Local0 != 0xfa) {
|
||||
Local0 = MRG0
|
||||
Sleep(10)
|
||||
}
|
||||
}
|
||||
|
||||
//Init
|
||||
Method (ITZE, 0)
|
||||
{
|
||||
MRG0 = 0
|
||||
MRG1 = 0xb5
|
||||
MRG2 = 0
|
||||
MSTI = 0x96
|
||||
WACK()
|
||||
|
||||
MRG0 = 0
|
||||
MRG1 = 0
|
||||
MRG2 = 0
|
||||
MSTI = 0x80
|
||||
WACK()
|
||||
|
||||
Local0 = MRG2 | 0x01
|
||||
|
||||
MRG0 = 0
|
||||
MRG1 = 0
|
||||
MRG2 = Local0
|
||||
MSTI = 0x81
|
||||
WACK()
|
||||
}
|
||||
|
||||
//Sleep
|
||||
Method (IMSP, 0)
|
||||
{
|
||||
MRG0 = 0
|
||||
MRG1 = 0xb5
|
||||
MRG2 = 0
|
||||
MSTI = 0x96
|
||||
WACK()
|
||||
|
||||
MRG0 = 0
|
||||
MRG1 = 1
|
||||
MRG2 = 0
|
||||
MSTI = 0x98
|
||||
WACK()
|
||||
|
||||
MRG0 = 0
|
||||
MRG1 = 0xb4
|
||||
MRG2 = 0
|
||||
MSTI = 0x96
|
||||
WACK()
|
||||
}
|
||||
|
||||
//Wake
|
||||
Method (IMWK, 0)
|
||||
{
|
||||
MRG0 = 0
|
||||
MRG1 = 0xb5
|
||||
MRG2 = 0
|
||||
MSTI = 0x96
|
||||
WACK()
|
||||
|
||||
MRG0 = 0
|
||||
MRG1 = 0
|
||||
MRG2 = 0
|
||||
MSTI = 0x80
|
||||
WACK()
|
||||
|
||||
Local0 = MRG2 | 0x01
|
||||
|
||||
MRG0 = 0
|
||||
MRG1 = 0
|
||||
MRG2 = Local0
|
||||
MSTI = 0x81
|
||||
WACK()
|
||||
}
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Scope(\_GPE) { /* Start Scope GPE */
|
||||
|
||||
/* General event 3 */
|
||||
Method(_L03) {
|
||||
/* DBGO("\\_GPE\\_L00\n") */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Legacy PM event */
|
||||
Method(_L08) {
|
||||
/* DBGO("\\_GPE\\_L08\n") */
|
||||
}
|
||||
|
||||
/* Temp warning (TWarn) event */
|
||||
Method(_L09) {
|
||||
/* DBGO("\\_GPE\\_L09\n") */
|
||||
/* Notify (\_TZ.TZ00, 0x80) */
|
||||
}
|
||||
|
||||
/* USB controller PME# */
|
||||
Method(_L0B) {
|
||||
/* DBGO("\\_GPE\\_L0B\n") */
|
||||
Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* ExtEvent0 SCI event */
|
||||
Method(_L10) {
|
||||
/* DBGO("\\_GPE\\_L10\n") */
|
||||
}
|
||||
|
||||
/* ExtEvent1 SCI event */
|
||||
Method(_L11) {
|
||||
/* DBGO("\\_GPE\\_L11\n") */
|
||||
}
|
||||
|
||||
/* GPIO0 or GEvent8 event */
|
||||
Method(_L18) {
|
||||
/* DBGO("\\_GPE\\_L18\n") */
|
||||
Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Azalia SCI event */
|
||||
Method(_L1B) {
|
||||
/* DBGO("\\_GPE\\_L1B\n") */
|
||||
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
} /* End Scope GPE */
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
|
||||
/* AcpiGpe0Blk */
|
||||
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
|
||||
Field(GP0B, ByteAcc, NoLock, Preserve) {
|
||||
, 11,
|
||||
USBS, 1,
|
||||
}
|
||||
|
|
@ -1,169 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - F16 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
|
||||
/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
|
||||
Package(){0x0001FFFF, 0, INTB, 0 },
|
||||
Package(){0x0001FFFF, 1, INTC, 0 },
|
||||
|
||||
/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
|
||||
/* FCH devices */
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
|
||||
/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
|
||||
/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
|
||||
Package(){0x0012FFFF, 0, INTC, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0013FFFF, 0, INTC, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0016FFFF, 0, INTC, 0 },
|
||||
Package(){0x0016FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
|
||||
Package(){0x0010FFFF, 0, INTC, 0 },
|
||||
Package(){0x0010FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 17 - SATA controller */
|
||||
Package(){0x0011FFFF, 0, INTD, 0 },
|
||||
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - F15 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
|
||||
Package(){0x0001FFFF, 0, 0, 44 },
|
||||
Package(){0x0001FFFF, 1, 0, 45 },
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridges */
|
||||
Package(){0x0002FFFF, 0, 0, 24 },
|
||||
Package(){0x0002FFFF, 1, 0, 25 },
|
||||
Package(){0x0002FFFF, 2, 0, 26 },
|
||||
Package(){0x0002FFFF, 3, 0, 27 },
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
|
||||
/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
|
||||
Package(){0x0012FFFF, 0, 0, 18 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 17 },
|
||||
|
||||
Package(){0x0016FFFF, 0, 0, 18 },
|
||||
Package(){0x0016FFFF, 1, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
|
||||
Package(){0x0010FFFF, 0, 0, 0x12},
|
||||
Package(){0x0010FFFF, 1, 0, 0x11},
|
||||
|
||||
/* Bus 0, Dev 17 - SATA controller */
|
||||
Package(){0x0011FFFF, 0, 0, 19 },
|
||||
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS2, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
/* GFX */
|
||||
Name(PS4, Package(){
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 24 },
|
||||
Package(){0x0000FFFF, 1, 0, 25 },
|
||||
Package(){0x0000FFFF, 2, 0, 26 },
|
||||
Package(){0x0000FFFF, 3, 0, 27 },
|
||||
})
|
||||
|
||||
/* GPP 0 */
|
||||
Name(PS5, Package(){
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APS5, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 28 },
|
||||
Package(){0x0000FFFF, 1, 0, 29 },
|
||||
Package(){0x0000FFFF, 2, 0, 30 },
|
||||
Package(){0x0000FFFF, 3, 0, 31 },
|
||||
})
|
||||
|
||||
/* GPP 1 */
|
||||
Name(PS6, Package(){
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS6, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 32 },
|
||||
Package(){0x0000FFFF, 1, 0, 33 },
|
||||
Package(){0x0000FFFF, 2, 0, 34 },
|
||||
Package(){0x0000FFFF, 3, 0, 35 },
|
||||
})
|
||||
|
||||
/* GPP 2 */
|
||||
Name(PS7, Package(){
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APS7, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 36 },
|
||||
Package(){0x0000FFFF, 1, 0, 37 },
|
||||
Package(){0x0000FFFF, 2, 0, 38 },
|
||||
Package(){0x0000FFFF, 3, 0, 39 },
|
||||
})
|
||||
|
||||
/* GPP 3 */
|
||||
Name(PS8, Package(){
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS8, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 40 },
|
||||
Package(){0x0000FFFF, 1, 0, 41 },
|
||||
Package(){0x0000FFFF, 2, 0, 42 },
|
||||
Package(){0x0000FFFF, 3, 0, 43 },
|
||||
})
|
||||
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Reference in New Issue