soc/amd/common: Move PCIe CLKREQ programming under fsp

CLKREQ programming as currently implemented is completely dependent on
FSP DXIO descriptors, so move under common/fsp/pci and rename the
Kconfig to reflect the move.

TEST=build google/{guybrush, skyrim, myst}

Change-Id: I87b53d092ddc367b134c25949f9da7670a6a1d88
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit is contained in:
Matt DeVillier 2023-11-13 20:57:12 -06:00 committed by Felix Held
parent fca7fd2a73
commit 6bb0f8aaa4
8 changed files with 12 additions and 14 deletions

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@ -55,7 +55,6 @@ config SOC_AMD_CEZANNE
select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM
select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select SOC_AMD_COMMON_BLOCK_PSP_GEN2
@ -74,6 +73,7 @@ config SOC_AMD_CEZANNE
select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_DMI_TABLES
select SOC_AMD_COMMON_FSP_PCI select SOC_AMD_COMMON_FSP_PCI
select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
select SOC_AMD_COMMON_FSP_PRELOAD_FSPS select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
select SOC_AMD_COMMON_BLOCK_XHCI select SOC_AMD_COMMON_BLOCK_XHCI
select SSE2 select SSE2

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@ -16,10 +16,3 @@ config SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
depends on SOC_AMD_COMMON_BLOCK_PCI depends on SOC_AMD_COMMON_BLOCK_PCI
help help
Select this option to use AMD common PCIe GPP driver. Select this option to use AMD common PCIe GPP driver.
config SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
bool
depends on SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
help
This option includes code to disable PCIe clock request if the corresponding
PCIe device is disabled.

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@ -5,7 +5,6 @@ ramstage-y += amd_pci_util.c
ramstage-y += pci_routing_info.c ramstage-y += pci_routing_info.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_prt.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_prt.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER) += pcie_gpp.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER) += pcie_gpp.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ) += pcie_clk_req.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI

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@ -3,3 +3,10 @@ config SOC_AMD_COMMON_FSP_PCI
select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI
help help
This option enabled FSP to provide common PCI functions. This option enabled FSP to provide common PCI functions.
config SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
bool
depends on SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
help
This option includes code to disable PCIe clock request if the corresponding
PCIe device is disabled.

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@ -1,6 +1,5 @@
## SPDX-License-Identifier: GPL-2.0-only ## SPDX-License-Identifier: GPL-2.0-only
ifeq ($(CONFIG_SOC_AMD_COMMON_FSP_PCI),y)
ramstage-y += pci_routing_info.c ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_PCI) += pci_routing_info.c
endif # CONFIG_SOC_AMD_COMMON_FSP_PCI ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_PCIE_CLK_REQ) += pcie_clk_req.c

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@ -61,7 +61,6 @@ config SOC_AMD_REMBRANDT_BASE
select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM
select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select SOC_AMD_COMMON_BLOCK_PSP_GEN2
@ -82,6 +81,7 @@ config SOC_AMD_REMBRANDT_BASE
select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_DMI_TABLES
select SOC_AMD_COMMON_FSP_PCI select SOC_AMD_COMMON_FSP_PCI
select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
select SOC_AMD_COMMON_FSP_PRELOAD_FSPS select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
select SSE2 select SSE2
select UDK_2017_BINDING select UDK_2017_BINDING

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@ -60,7 +60,6 @@ config SOC_AMD_PHOENIX
select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM
select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct
@ -80,6 +79,7 @@ config SOC_AMD_PHOENIX
select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_DMI_TABLES
select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct
select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
select SOC_AMD_COMMON_FSP_PRELOAD_FSPS select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
select SSE2 select SSE2
select UDK_2017_BINDING select UDK_2017_BINDING